Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11629898 [patent_doc_number] => 20170140087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'Method and device for chip integration and storage medium' [patent_app_type] => utility [patent_app_number] => 15/322420 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3538 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322420 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/322420
Method and device for chip integration and storage medium Nov 17, 2014 Abandoned
Array ( [id] => 11239259 [patent_doc_number] => 09465903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Programmable IC design creation using circuit board data' [patent_app_type] => utility [patent_app_number] => 14/546684 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6367 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546684 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/546684
Programmable IC design creation using circuit board data Nov 17, 2014 Issued
Array ( [id] => 11482544 [patent_doc_number] => 09589092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for co-designing flip-chip and interposer' [patent_app_type] => utility [patent_app_number] => 14/546238 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546238 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/546238
Method for co-designing flip-chip and interposer Nov 17, 2014 Issued
Array ( [id] => 13753149 [patent_doc_number] => 10169522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Methods and system for model-based generic matching and tuning [patent_app_type] => utility [patent_app_number] => 14/543326 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9670 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543326
Methods and system for model-based generic matching and tuning Nov 16, 2014 Issued
Array ( [id] => 11207162 [patent_doc_number] => 09436790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-06 [patent_title] => 'Systems and methods for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 14/541839 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2467 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541839 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541839
Systems and methods for integrated circuit design Nov 13, 2014 Issued
Array ( [id] => 10821375 [patent_doc_number] => 20160167539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'CONTROL SYSTEM FOR ELECTRIC VEHICLE CHARGING STATION AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/896170 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7470 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14896170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/896170
Control system for electric vehicle charging station and method thereof Oct 30, 2014 Issued
Array ( [id] => 11320998 [patent_doc_number] => 09519742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Support device, semiconductor device, and non-transitory computer readable medium' [patent_app_type] => utility [patent_app_number] => 14/518941 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 13554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518941 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518941
Support device, semiconductor device, and non-transitory computer readable medium Oct 19, 2014 Issued
Array ( [id] => 10764333 [patent_doc_number] => 20160110489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHODS, APPARATUS, AND SYSTEM FOR USING FILLER CELLS IN DESIGN OF INTEGRATED CIRCUIT DEVICES' [patent_app_type] => utility [patent_app_number] => 14/518939 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518939
Methods, apparatus, and system for using filler cells in design of integrated circuit devices Oct 19, 2014 Issued
Array ( [id] => 11214006 [patent_doc_number] => 09443044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Determining a quality parameter for a verification environment' [patent_app_type] => utility [patent_app_number] => 14/518364 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518364 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518364
Determining a quality parameter for a verification environment Oct 19, 2014 Issued
Array ( [id] => 9814710 [patent_doc_number] => 20150026655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'DETERMINING A SET OF TIMING PATHS FOR CREATING A CIRCUIT ABSTRACTION' [patent_app_type] => utility [patent_app_number] => 14/508523 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3821 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14508523 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/508523
Determining a set of timing paths for creating a circuit abstraction Oct 6, 2014 Issued
Array ( [id] => 13069095 [patent_doc_number] => 10055327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Evaluating fairness in devices under test [patent_app_type] => utility [patent_app_number] => 14/501709 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501709 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501709
Evaluating fairness in devices under test Sep 29, 2014 Issued
Array ( [id] => 10724697 [patent_doc_number] => 20160070845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'CRITICAL REGION IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 14/481154 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3834 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481154 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481154
Critical region identification Sep 8, 2014 Issued
Array ( [id] => 10724698 [patent_doc_number] => 20160070846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SYSTEM FOR TESTING IC DESIGN' [patent_app_type] => utility [patent_app_number] => 14/481899 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481899
SYSTEM FOR TESTING IC DESIGN Sep 8, 2014 Abandoned
Array ( [id] => 14601699 [patent_doc_number] => 10354042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Selectively reducing graph based analysis pessimism [patent_app_type] => utility [patent_app_number] => 14/480543 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9389 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480543
Selectively reducing graph based analysis pessimism Sep 7, 2014 Issued
Array ( [id] => 10610185 [patent_doc_number] => 09330220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-03 [patent_title] => 'Clock region partitioning and clock routing' [patent_app_type] => utility [patent_app_number] => 14/467908 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 12468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467908 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467908
Clock region partitioning and clock routing Aug 24, 2014 Issued
Array ( [id] => 10969925 [patent_doc_number] => 20140372959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS' [patent_app_type] => utility [patent_app_number] => 14/467327 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467327 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467327
Analytical model for predicting current mismatch in metal oxide semiconductor arrays Aug 24, 2014 Issued
Array ( [id] => 9866874 [patent_doc_number] => 20150046894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Constrained Placement of Connected Elements' [patent_app_type] => utility [patent_app_number] => 14/453585 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7420 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453585
Constrained placement of connected elements Aug 5, 2014 Issued
Array ( [id] => 11246916 [patent_doc_number] => 09472967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Power management system and method for a portable device' [patent_app_type] => utility [patent_app_number] => 14/448509 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6707 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14448509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/448509
Power management system and method for a portable device Jul 30, 2014 Issued
Array ( [id] => 11230453 [patent_doc_number] => 09457672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Charging apparatus with dynamical charging power and method of operating the same' [patent_app_type] => utility [patent_app_number] => 14/448289 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3803 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14448289 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/448289
Charging apparatus with dynamical charging power and method of operating the same Jul 30, 2014 Issued
Array ( [id] => 10370758 [patent_doc_number] => 20150255763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'POWER SUPPLY DEVICE AND METHOD OF ASSEMBLING THE POWER SUPPLY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/448681 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2483 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14448681 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/448681
Power supply device and method of assembling the power supply device Jul 30, 2014 Issued
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