Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11044116 [patent_doc_number] => 20160241072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'CHARGE/DISCHARGE CONTROL DEVICE AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/025468 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9415 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15025468 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/025468
CHARGE/DISCHARGE CONTROL DEVICE AND PROGRAM Dec 9, 2013 Abandoned
Array ( [id] => 9564056 [patent_doc_number] => 20140181769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'NETLIST CELL IDENTIFICATION AND CLASSIFICATION TO REDUCE POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 14/102167 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102167
Netlist cell identification and classification to reduce power consumption Dec 9, 2013 Issued
Array ( [id] => 10099074 [patent_doc_number] => 09135387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Data processing apparatus including reconfiguarable logic circuit' [patent_app_type] => utility [patent_app_number] => 14/095317 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 10773 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095317 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/095317
Data processing apparatus including reconfiguarable logic circuit Dec 2, 2013 Issued
Array ( [id] => 10418723 [patent_doc_number] => 20150303734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'Induction Charger' [patent_app_type] => utility [patent_app_number] => 14/646070 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4305 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14646070 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/646070
Induction Charger Nov 19, 2013 Abandoned
Array ( [id] => 10258316 [patent_doc_number] => 20150143313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'Grouping Layout Features For Directed Self Assembly' [patent_app_type] => utility [patent_app_number] => 14/083045 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5226 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083045
Grouping layout features for directed self assembly Nov 17, 2013 Issued
Array ( [id] => 10124514 [patent_doc_number] => 09158874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Formal verification coverage metrics of covered events for circuit design properties' [patent_app_type] => utility [patent_app_number] => 14/073787 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073787
Formal verification coverage metrics of covered events for circuit design properties Nov 5, 2013 Issued
Array ( [id] => 9893602 [patent_doc_number] => 20150048801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'METHOD AND SYSTEM FOR ENERGY STORAGE CAPACITY ESTIMATION OF BATTER CELLS' [patent_app_type] => utility [patent_app_number] => 14/072824 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/072824
Method and system for energy storage capacity estimation of battery cells Nov 5, 2013 Issued
Array ( [id] => 9601101 [patent_doc_number] => 20140197783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'APPARATUS AND METHOD FOR TRANSMITTING POWER AND TRANSCEIVING DATA USING MUTUAL RESONANCE, AND APPARATUS AND METHOD FOR RECEIVING POWER AND TRANSCEIVING DATA USING MUTUAL RESONANCE' [patent_app_type] => utility [patent_app_number] => 14/073025 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15538 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073025
Apparatus and method for transmitting power and transceiving data using mutual resonance, and apparatus and method for receiving power and transceiving data using mutual resonance Nov 5, 2013 Issued
Array ( [id] => 9460855 [patent_doc_number] => 20140125280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'METHOD AND SYSTEM FOR CHARGING ELECTRIC VEHICLES IN AGGREGATION' [patent_app_type] => utility [patent_app_number] => 14/072203 [patent_app_country] => US [patent_app_date] => 2013-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6297 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/072203
Method and system for charging electric vehicles in aggregation Nov 4, 2013 Issued
Array ( [id] => 9891716 [patent_doc_number] => 08977991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Method and system for replacing a pattern in a layout' [patent_app_type] => utility [patent_app_number] => 14/068006 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068006 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068006
Method and system for replacing a pattern in a layout Oct 30, 2013 Issued
Array ( [id] => 10092253 [patent_doc_number] => 09129078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages' [patent_app_type] => utility [patent_app_number] => 14/067720 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 48 [patent_no_of_words] => 20920 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/067720
Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages Oct 29, 2013 Issued
Array ( [id] => 9520731 [patent_doc_number] => 20140157223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/060162 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13821 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/060162
CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS Oct 21, 2013 Abandoned
Array ( [id] => 10085478 [patent_doc_number] => 09122826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-01 [patent_title] => 'Method and apparatus for performing compilation using multiple design flows' [patent_app_type] => utility [patent_app_number] => 14/052210 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6450 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052210 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052210
Method and apparatus for performing compilation using multiple design flows Oct 10, 2013 Issued
Array ( [id] => 9500262 [patent_doc_number] => 08739103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Techniques for placement in highly constrained architectures' [patent_app_type] => utility [patent_app_number] => 14/050105 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050105
Techniques for placement in highly constrained architectures Oct 8, 2013 Issued
Array ( [id] => 10215942 [patent_doc_number] => 20150100934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'INTEGRATED TRANSFORMER SYNTHESIS AND OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/045305 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4234 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045305
System and method for integrated transformer synthesis and optimization using constrained optimization problem Oct 2, 2013 Issued
Array ( [id] => 9283190 [patent_doc_number] => 20140033158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'Multiple Level Spine Routing' [patent_app_type] => utility [patent_app_number] => 14/043689 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4108 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043689 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043689
Multiple level spine routing Sep 30, 2013 Issued
Array ( [id] => 9283196 [patent_doc_number] => 20140033164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'MUTUAL INDUCTANCE EXTRACTION USING DIPOLE APPROXIMATIONS' [patent_app_type] => utility [patent_app_number] => 14/042279 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16358 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042279
Mutual inductance extraction using dipole approximations Sep 29, 2013 Issued
Array ( [id] => 9386397 [patent_doc_number] => 20140089880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'METHOD AND SYSTEM TO FIX EARLY MODE SLACKS IN A CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/035125 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12032 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035125 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/035125
Method and system to fix early mode slacks in a circuit design Sep 23, 2013 Issued
Array ( [id] => 9225146 [patent_doc_number] => 20140019921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL' [patent_app_type] => utility [patent_app_number] => 14/026648 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5174 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14026648 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/026648
Soft error and radiation hardened sequential logic cell Sep 12, 2013 Issued
Array ( [id] => 10901661 [patent_doc_number] => 08924906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Determining a design attribute by estimation and by calibration of estimated value' [patent_app_type] => utility [patent_app_number] => 14/016915 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016915 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016915
Determining a design attribute by estimation and by calibration of estimated value Sep 2, 2013 Issued
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