
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9071313
[patent_doc_number] => 20130263069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-03
[patent_title] => 'OPTIMIZING LOGIC SYNTHESIS FOR ENVIRONMENTAL INSENSITIVITY'
[patent_app_type] => utility
[patent_app_number] => 13/432935
[patent_app_country] => US
[patent_app_date] => 2012-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6897
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432935
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/432935 | Optimizing logic synthesis for environmental insensitivity | Mar 27, 2012 | Issued |
Array
(
[id] => 9579030
[patent_doc_number] => 08769466
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-01
[patent_title] => 'Implementation design support method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/427945
[patent_app_country] => US
[patent_app_date] => 2012-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 30
[patent_no_of_words] => 13634
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427945
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/427945 | Implementation design support method and apparatus | Mar 22, 2012 | Issued |
Array
(
[id] => 10550561
[patent_doc_number] => 09275187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-01
[patent_title] => 'Programmable test chip, system and method for characterization of integrated circuit fabrication processes'
[patent_app_type] => utility
[patent_app_number] => 13/424025
[patent_app_country] => US
[patent_app_date] => 2012-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 7349
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424025
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/424025 | Programmable test chip, system and method for characterization of integrated circuit fabrication processes | Mar 18, 2012 | Issued |
Array
(
[id] => 9527701
[patent_doc_number] => 08751992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-10
[patent_title] => 'Power supply wiring structure'
[patent_app_type] => utility
[patent_app_number] => 13/420945
[patent_app_country] => US
[patent_app_date] => 2012-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 6587
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 353
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420945
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/420945 | Power supply wiring structure | Mar 14, 2012 | Issued |
Array
(
[id] => 9316884
[patent_doc_number] => 20140049222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'Method for Opportunistically Balancing Charge Between Battery Cells'
[patent_app_type] => utility
[patent_app_number] => 14/003051
[patent_app_country] => US
[patent_app_date] => 2012-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10950
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14003051
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/003051 | Method for opportunistically balancing charge between battery cells | Mar 6, 2012 | Issued |
Array
(
[id] => 8678841
[patent_doc_number] => 08386978
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-02-26
[patent_title] => 'Software and systems for physical layout estimation'
[patent_app_type] => utility
[patent_app_number] => 13/372507
[patent_app_country] => US
[patent_app_date] => 2012-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 7297
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372507
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/372507 | Software and systems for physical layout estimation | Feb 13, 2012 | Issued |
Array
(
[id] => 8678841
[patent_doc_number] => 08386978
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-02-26
[patent_title] => 'Software and systems for physical layout estimation'
[patent_app_type] => utility
[patent_app_number] => 13/372507
[patent_app_country] => US
[patent_app_date] => 2012-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 7297
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372507
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/372507 | Software and systems for physical layout estimation | Feb 13, 2012 | Issued |
Array
(
[id] => 9992786
[patent_doc_number] => 09038007
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-19
[patent_title] => 'Prediction of dynamic current waveform and spectrum in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/365567
[patent_app_country] => US
[patent_app_date] => 2012-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 4961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365567
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/365567 | Prediction of dynamic current waveform and spectrum in a semiconductor device | Feb 2, 2012 | Issued |
Array
(
[id] => 9130352
[patent_doc_number] => 08578309
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Format conversion from value change dump (VCD) to universal verification methodology (UVM)'
[patent_app_type] => utility
[patent_app_number] => 13/362415
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5589
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362415
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/362415 | Format conversion from value change dump (VCD) to universal verification methodology (UVM) | Jan 30, 2012 | Issued |
Array
(
[id] => 8588859
[patent_doc_number] => 20130007680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'Coverage Based Pairwise Test Set Generation for Verification of Electronic Designs'
[patent_app_type] => utility
[patent_app_number] => 13/363355
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3089
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363355
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363355 | Coverage Based Pairwise Test Set Generation for Verification of Electronic Designs | Jan 30, 2012 | Abandoned |
Array
(
[id] => 10151039
[patent_doc_number] => 09183330
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-10
[patent_title] => 'Estimation of power and thermal profiles'
[patent_app_type] => utility
[patent_app_number] => 13/363345
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6187
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363345
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363345 | Estimation of power and thermal profiles | Jan 30, 2012 | Issued |
Array
(
[id] => 9458720
[patent_doc_number] => 08719747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Single event upset mitigation for electronic design synthesis'
[patent_app_type] => utility
[patent_app_number] => 13/362605
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4104
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362605
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/362605 | Single event upset mitigation for electronic design synthesis | Jan 30, 2012 | Issued |
Array
(
[id] => 9089536
[patent_doc_number] => 08560984
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-15
[patent_title] => 'Methods and systsm for physical layout estimation'
[patent_app_type] => utility
[patent_app_number] => 13/357390
[patent_app_country] => US
[patent_app_date] => 2012-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 7299
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357390
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/357390 | Methods and systsm for physical layout estimation | Jan 23, 2012 | Issued |
Array
(
[id] => 9500237
[patent_doc_number] => 08739078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications'
[patent_app_type] => utility
[patent_app_number] => 13/353035
[patent_app_country] => US
[patent_app_date] => 2012-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 10401
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353035
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/353035 | Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications | Jan 17, 2012 | Issued |
Array
(
[id] => 8906603
[patent_doc_number] => 20130174107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'DESIGN TOOL FOR GLITCH REMOVAL'
[patent_app_type] => utility
[patent_app_number] => 13/340455
[patent_app_country] => US
[patent_app_date] => 2011-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3008
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340455
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/340455 | Tool for glitch removal | Dec 28, 2011 | Issued |
Array
(
[id] => 8763386
[patent_doc_number] => 08423925
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-04-16
[patent_title] => 'System and method for compressed post-OPC data'
[patent_app_type] => utility
[patent_app_number] => 13/330580
[patent_app_country] => US
[patent_app_date] => 2011-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6878
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330580
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/330580 | System and method for compressed post-OPC data | Dec 18, 2011 | Issued |
Array
(
[id] => 8763385
[patent_doc_number] => 08423924
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-04-16
[patent_title] => 'System and method for compressed post-OPC data'
[patent_app_type] => utility
[patent_app_number] => 13/330566
[patent_app_country] => US
[patent_app_date] => 2011-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6837
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330566
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/330566 | System and method for compressed post-OPC data | Dec 18, 2011 | Issued |
Array
(
[id] => 10132553
[patent_doc_number] => 09166399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-20
[patent_title] => 'Lithium battery protection circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/807635
[patent_app_country] => US
[patent_app_date] => 2011-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7333
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13807635
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/807635 | Lithium battery protection circuitry | Nov 28, 2011 | Issued |
Array
(
[id] => 9276126
[patent_doc_number] => 08640074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-28
[patent_title] => 'Digital circuit block having reducing supply voltage drop and method for constructing the same'
[patent_app_type] => utility
[patent_app_number] => 13/298315
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3482
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298315
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/298315 | Digital circuit block having reducing supply voltage drop and method for constructing the same | Nov 16, 2011 | Issued |
Array
(
[id] => 9579033
[patent_doc_number] => 08769470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-01
[patent_title] => 'Timing closure in chip design'
[patent_app_type] => utility
[patent_app_number] => 13/296555
[patent_app_country] => US
[patent_app_date] => 2011-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7992
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296555
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/296555 | Timing closure in chip design | Nov 14, 2011 | Issued |