Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8763384 [patent_doc_number] => 08423923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Optical proximity correction method' [patent_app_type] => utility [patent_app_number] => 13/186475 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2675 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186475
Optical proximity correction method Jul 19, 2011 Issued
Array ( [id] => 8033891 [patent_doc_number] => 08146041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Latch based optimization during implementation of circuit designs for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 13/180782 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6088 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146041.pdf [firstpage_image] =>[orig_patent_app_number] => 13180782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180782
Latch based optimization during implementation of circuit designs for programmable logic devices Jul 11, 2011 Issued
Array ( [id] => 9264999 [patent_doc_number] => 20130346928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'METHOD FOR PROTECTING RTL IP CORE' [patent_app_type] => utility [patent_app_number] => 13/977205 [patent_app_country] => US [patent_app_date] => 2011-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3045 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977205
METHOD FOR PROTECTING RTL IP CORE Jun 24, 2011 Abandoned
Array ( [id] => 7820033 [patent_doc_number] => 20120066653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'DOSE-DATA GENERATING APPARATUS, DOSE-DATA GENERATING METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/168215 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066653.pdf [firstpage_image] =>[orig_patent_app_number] => 13168215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/168215
Dose-data generating apparatus, dose-data generating method, and manufacturing method of semiconductor device Jun 23, 2011 Issued
Array ( [id] => 7722146 [patent_doc_number] => 20120011481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'Hierarchical Finite State Machine Generation For Power State Behavior in an Electronic Design' [patent_app_type] => utility [patent_app_number] => 13/167415 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4281 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011481.pdf [firstpage_image] =>[orig_patent_app_number] => 13167415 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167415
Hierarchical finite state machine generation for power state behavior in an electronic design Jun 22, 2011 Issued
Array ( [id] => 8059405 [patent_doc_number] => 20120079444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'COMPUTER AIDED DESIGN SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/163695 [patent_app_country] => US [patent_app_date] => 2011-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079444.pdf [firstpage_image] =>[orig_patent_app_number] => 13163695 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163695
Computer aided design system and method Jun 18, 2011 Issued
Array ( [id] => 7665162 [patent_doc_number] => 20110314431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'METHOD OF ETCH PROXIMITY CORRECTION AND METHOD OF CREATING PHOTOMASK LAYOUT USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/161985 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161985 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161985
Method of etch proximity correction and method of creating photomask layout using the same Jun 15, 2011 Issued
Array ( [id] => 8536234 [patent_doc_number] => 08312400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Verification supporting system' [patent_app_type] => utility [patent_app_number] => 13/157534 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 9878 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13157534 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/157534
Verification supporting system Jun 9, 2011 Issued
Array ( [id] => 8512107 [patent_doc_number] => 20120311515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs' [patent_app_type] => utility [patent_app_number] => 13/151295 [patent_app_country] => US [patent_app_date] => 2011-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9108 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151295
Method for performing a parallel static timing analysis using thread-specific sub-graphs Jun 1, 2011 Issued
Array ( [id] => 8512106 [patent_doc_number] => 20120311514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'Decentralized Dynamically Scheduled Parallel Static Timing Analysis' [patent_app_type] => utility [patent_app_number] => 13/150445 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6647 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150445 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/150445
Decentralized dynamically scheduled parallel static timing analysis May 31, 2011 Issued
Array ( [id] => 8645787 [patent_doc_number] => 08370786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Methods and software for placement improvement based on global routing' [patent_app_type] => utility [patent_app_number] => 13/149275 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149275
Methods and software for placement improvement based on global routing May 30, 2011 Issued
Array ( [id] => 7563104 [patent_doc_number] => 20110276938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'POWER SUPPLY OPTIMIZATION FOR ELECTRICAL CIRCUITS DESIGNED OVER THE INTERNET' [patent_app_type] => utility [patent_app_number] => 13/104552 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 69 [patent_no_of_words] => 16141 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276938.pdf [firstpage_image] =>[orig_patent_app_number] => 13104552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104552
Power supply optimization for electrical circuits designed over the internet May 9, 2011 Issued
Array ( [id] => 6020847 [patent_doc_number] => 20110225562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 13/100584 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6020 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225562.pdf [firstpage_image] =>[orig_patent_app_number] => 13100584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100584
Compact model methodology for PC landing pad lithographic rounding impact on device performance May 3, 2011 Issued
Array ( [id] => 6052608 [patent_doc_number] => 20110209105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'Photolithographic mask correction' [patent_app_type] => utility [patent_app_number] => 13/066832 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7687 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20110209105.pdf [firstpage_image] =>[orig_patent_app_number] => 13066832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/066832
Photolithographic mask correction Apr 24, 2011 Abandoned
Array ( [id] => 11299894 [patent_doc_number] => 09507902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Simultaneous multi-layer fill generation' [patent_app_type] => utility [patent_app_number] => 13/093828 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12398 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093828
Simultaneous multi-layer fill generation Apr 24, 2011 Issued
Array ( [id] => 11299894 [patent_doc_number] => 09507902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Simultaneous multi-layer fill generation' [patent_app_type] => utility [patent_app_number] => 13/093828 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12398 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093828
Simultaneous multi-layer fill generation Apr 24, 2011 Issued
Array ( [id] => 11299894 [patent_doc_number] => 09507902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Simultaneous multi-layer fill generation' [patent_app_type] => utility [patent_app_number] => 13/093828 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12398 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093828
Simultaneous multi-layer fill generation Apr 24, 2011 Issued
Array ( [id] => 11299894 [patent_doc_number] => 09507902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Simultaneous multi-layer fill generation' [patent_app_type] => utility [patent_app_number] => 13/093828 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12398 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093828
Simultaneous multi-layer fill generation Apr 24, 2011 Issued
Array ( [id] => 8331712 [patent_doc_number] => 08239789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'System and method of predicting problematic areas for lithography in a circuit design' [patent_app_type] => utility [patent_app_number] => 13/080148 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5831 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080148
System and method of predicting problematic areas for lithography in a circuit design Apr 4, 2011 Issued
Array ( [id] => 8787189 [patent_doc_number] => 08434045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-30 [patent_title] => 'System and method of providing a memory hierarchy' [patent_app_type] => utility [patent_app_number] => 13/047784 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 58 [patent_no_of_words] => 20610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13047784 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047784
System and method of providing a memory hierarchy Mar 13, 2011 Issued
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