Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8716262 [patent_doc_number] => 08402415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Layout device and layout method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/039955 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12132 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039955
Layout device and layout method of semiconductor integrated circuit Mar 2, 2011 Issued
Array ( [id] => 8789387 [patent_doc_number] => 20130106356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'BATTERY CONTROL CIRCUIT AND BATTERY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/807487 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 16470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13807487 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/807487
Battery control circuit and battery device Feb 27, 2011 Issued
Array ( [id] => 8595003 [patent_doc_number] => 08352886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method for the reproducible determination of the position of structures on a mask with a pellicle frame' [patent_app_type] => utility [patent_app_number] => 13/030665 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5476 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13030665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/030665
Method for the reproducible determination of the position of structures on a mask with a pellicle frame Feb 17, 2011 Issued
Array ( [id] => 8561935 [patent_doc_number] => 08336006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Mask-layout creating method, apparatus therefor, and computer program product' [patent_app_type] => utility [patent_app_number] => 13/028525 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 9549 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13028525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/028525
Mask-layout creating method, apparatus therefor, and computer program product Feb 15, 2011 Issued
Array ( [id] => 9886137 [patent_doc_number] => 08972923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Method and apparatus and software code for generating a hardware stream processor design' [patent_app_type] => utility [patent_app_number] => 13/023275 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023275
Method and apparatus and software code for generating a hardware stream processor design Feb 7, 2011 Issued
Array ( [id] => 8615670 [patent_doc_number] => 20130020982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'EQUALIZATION SYSTEM FOR ACCUMULATOR BATTERIES' [patent_app_type] => utility [patent_app_number] => 13/577185 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6606 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13577185 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/577185
EQUALIZATION SYSTEM FOR ACCUMULATOR BATTERIES Feb 3, 2011 Abandoned
Array ( [id] => 8636026 [patent_doc_number] => 20130027828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'INTERNAL TEMPERATURE ESTIMATION UNIT FOR BATTERY FOR ELECTRIC POWER TOOL, AND APPARATUS FOR ELECTRIC POWER TOOL' [patent_app_type] => utility [patent_app_number] => 13/640424 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11543 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13640424 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/640424
Internal temperature estimation unit for battery for electric power tool, and apparatus for electric power tool Feb 2, 2011 Issued
Array ( [id] => 8667685 [patent_doc_number] => 08381158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Verification computer product, method, and apparatus' [patent_app_type] => utility [patent_app_number] => 13/020615 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9331 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13020615 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020615
Verification computer product, method, and apparatus Feb 2, 2011 Issued
Array ( [id] => 6057680 [patent_doc_number] => 20110113396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF ESTIMATED VALUE' [patent_app_type] => utility [patent_app_number] => 13/007665 [patent_app_country] => US [patent_app_date] => 2011-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113396.pdf [firstpage_image] =>[orig_patent_app_number] => 13007665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007665
Determining a design attribute by estimation and by calibration of estimated value Jan 16, 2011 Issued
Array ( [id] => 9623434 [patent_doc_number] => 08793629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-29 [patent_title] => 'Method and apparatus for implementing carry chains on FPGA devices' [patent_app_type] => utility [patent_app_number] => 12/987519 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987519
Method and apparatus for implementing carry chains on FPGA devices Jan 9, 2011 Issued
Array ( [id] => 9891719 [patent_doc_number] => 08977994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-10 [patent_title] => 'Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints' [patent_app_type] => utility [patent_app_number] => 12/983247 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8307 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983247
Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints Dec 30, 2010 Issued
Array ( [id] => 8263404 [patent_doc_number] => 20120162834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Electrostatic Discharge (ESD) Protection Circuit and Method for Designing Thereof for Protection of Millimeter Wave Electrical Elements' [patent_app_type] => utility [patent_app_number] => 12/980085 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3310 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12980085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980085
Electrostatic discharge (ESD) protection circuit and method for designing thereof for protection of millimeter wave electrical elements Dec 27, 2010 Issued
Array ( [id] => 9585973 [patent_doc_number] => 08775984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Phase coherent differential structures' [patent_app_type] => utility [patent_app_number] => 12/979684 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2592 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979684 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979684
Phase coherent differential structures Dec 27, 2010 Issued
Array ( [id] => 9116338 [patent_doc_number] => 08572530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Method and apparatus for performing path-level skew optimization and analysis for a logic design' [patent_app_type] => utility [patent_app_number] => 12/928245 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8643 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12928245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/928245
Method and apparatus for performing path-level skew optimization and analysis for a logic design Dec 5, 2010 Issued
Array ( [id] => 9579017 [patent_doc_number] => 08769453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs' [patent_app_type] => utility [patent_app_number] => 12/916469 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12916469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916469
Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs Oct 28, 2010 Issued
Array ( [id] => 9289517 [patent_doc_number] => 08645875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Method for quantifying the manufacturing complexity of electrical designs' [patent_app_type] => utility [patent_app_number] => 12/914367 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4357 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914367 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914367
Method for quantifying the manufacturing complexity of electrical designs Oct 27, 2010 Issued
Array ( [id] => 9276118 [patent_doc_number] => 08640066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Multi-phase models for timing closure of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/897777 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 22638 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12897777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/897777
Multi-phase models for timing closure of integrated circuit designs Oct 3, 2010 Issued
Array ( [id] => 8924083 [patent_doc_number] => 08490032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Flash-based anti-aliasing techniques for high-accuracy high-efficiency mask synthesis' [patent_app_type] => utility [patent_app_number] => 12/892772 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7619 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12892772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892772
Flash-based anti-aliasing techniques for high-accuracy high-efficiency mask synthesis Sep 27, 2010 Issued
Array ( [id] => 9012591 [patent_doc_number] => 08527912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Digitally obtaining contours of fabricated polygons' [patent_app_type] => utility [patent_app_number] => 12/890336 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3517 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890336
Digitally obtaining contours of fabricated polygons Sep 23, 2010 Issued
Array ( [id] => 6141084 [patent_doc_number] => 20110010682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/879583 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6562 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20110010682.pdf [firstpage_image] =>[orig_patent_app_number] => 12879583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879583
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS Sep 9, 2010 Abandoned
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