Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6636001 [patent_doc_number] => 20100325597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 12/873112 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325597.pdf [firstpage_image] =>[orig_patent_app_number] => 12873112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873112
GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD Aug 30, 2010 Abandoned
Array ( [id] => 10046765 [patent_doc_number] => 09087164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Visualization of tradeoffs between circuit designs' [patent_app_type] => utility [patent_app_number] => 12/869201 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 15265 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869201
Visualization of tradeoffs between circuit designs Aug 25, 2010 Issued
Array ( [id] => 8357012 [patent_doc_number] => 20120212174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'QUICK CHARGING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/390355 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13390355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/390355
QUICK CHARGING DEVICE Aug 18, 2010 Abandoned
Array ( [id] => 6273228 [patent_doc_number] => 20100299648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC' [patent_app_type] => utility [patent_app_number] => 12/842670 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4084 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20100299648.pdf [firstpage_image] =>[orig_patent_app_number] => 12842670 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842670
Modular array defined by standard cell logic Jul 22, 2010 Issued
Array ( [id] => 6645116 [patent_doc_number] => 20100313177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'STATISTICAL ITERATIVE TIMING ANALYSIS OF CIRCUITS HAVING LATCHES AND/OR FEEDBACK LOOPS' [patent_app_type] => utility [patent_app_number] => 12/842268 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6174 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313177.pdf [firstpage_image] =>[orig_patent_app_number] => 12842268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842268
Statistical iterative timing analysis of circuits having latches and/or feedback loops Jul 22, 2010 Issued
Array ( [id] => 7747158 [patent_doc_number] => 20120023473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/840535 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023473.pdf [firstpage_image] =>[orig_patent_app_number] => 12840535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840535
Granular channel width for power optimization Jul 20, 2010 Issued
Array ( [id] => 8752260 [patent_doc_number] => 08418104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Automated synthesis of multi-channel circuits' [patent_app_type] => utility [patent_app_number] => 12/840243 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 49 [patent_no_of_words] => 15229 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12840243 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840243
Automated synthesis of multi-channel circuits Jul 19, 2010 Issued
Array ( [id] => 7575131 [patent_doc_number] => 20110270787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'VERIFICATION SUPPORT COMPUTER PRODUCT, APPARATUS, AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/838845 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12287 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20110270787.pdf [firstpage_image] =>[orig_patent_app_number] => 12838845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838845
Verification support computer product, apparatus, and method Jul 18, 2010 Issued
Array ( [id] => 6596245 [patent_doc_number] => 20100275171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'PACKAGE DESIGNS FOR FULLY FUNCTIONAL AND PARTIALLY FUNCTIONAL CHIPS' [patent_app_type] => utility [patent_app_number] => 12/832777 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4303 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275171.pdf [firstpage_image] =>[orig_patent_app_number] => 12832777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832777
Package designs for fully functional and partially functional chips Jul 7, 2010 Issued
Array ( [id] => 6100433 [patent_doc_number] => 20110004744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'DATA PROCESSING APPARATUS INCLUDING RECONFIGURABLE LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/831360 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10668 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004744.pdf [firstpage_image] =>[orig_patent_app_number] => 12831360 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831360
Data processing apparatus including reconfigurable logic circuit Jul 6, 2010 Issued
Array ( [id] => 8540614 [patent_doc_number] => 08316342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-20 [patent_title] => 'Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout' [patent_app_type] => utility [patent_app_number] => 12/792325 [patent_app_country] => US [patent_app_date] => 2010-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13363 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12792325 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/792325
Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout Jun 1, 2010 Issued
Array ( [id] => 8461014 [patent_doc_number] => 08296700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Analyzing method of semiconductor device, designing method thereof, and design supporting apparatus' [patent_app_type] => utility [patent_app_number] => 12/791535 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7898 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12791535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791535
Analyzing method of semiconductor device, designing method thereof, and design supporting apparatus May 31, 2010 Issued
Array ( [id] => 7582476 [patent_doc_number] => 20110296359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'METHOD AND COMPUTER-READABLE MEDIUM OF OPTICAL PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/788375 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1884 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296359.pdf [firstpage_image] =>[orig_patent_app_number] => 12788375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788375
Method and computer-readable medium of optical proximity correction May 26, 2010 Issued
Array ( [id] => 6088453 [patent_doc_number] => 20110145772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Modular Platform For Integrated Circuit Design Analysis And Verification' [patent_app_type] => utility [patent_app_number] => 12/780785 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15731 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145772.pdf [firstpage_image] =>[orig_patent_app_number] => 12780785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780785
Modular Platform For Integrated Circuit Design Analysis And Verification May 13, 2010 Abandoned
Array ( [id] => 7491758 [patent_doc_number] => 20110238233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZING CURRENT OVERLOAD PROTECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/774685 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238233.pdf [firstpage_image] =>[orig_patent_app_number] => 12774685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774685
System and method for optimizing current overload protection circuit May 4, 2010 Issued
Array ( [id] => 6596314 [patent_doc_number] => 20100275177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'METHOD FOR TRANSFERRING SELF-ASSEMBLED DUMMY PATTERN TO SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/772043 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7770 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275177.pdf [firstpage_image] =>[orig_patent_app_number] => 12772043 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772043
Method for transferring self-assembled dummy pattern to substrate Apr 29, 2010 Issued
Array ( [id] => 7504021 [patent_doc_number] => 20110265055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/767375 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265055.pdf [firstpage_image] =>[orig_patent_app_number] => 12767375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767375
Handling two-dimensional constraints in integrated circuit layout Apr 25, 2010 Issued
Array ( [id] => 6596194 [patent_doc_number] => 20100275168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/764165 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5495 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275168.pdf [firstpage_image] =>[orig_patent_app_number] => 12764165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764165
Method of semiconductor integrated circuit device and program Apr 20, 2010 Issued
Array ( [id] => 6231922 [patent_doc_number] => 20100264953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Soft Error Hard Electronic Circuit and Layout' [patent_app_type] => utility [patent_app_number] => 12/763139 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 7212 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264953.pdf [firstpage_image] =>[orig_patent_app_number] => 12763139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763139
Soft error hard electronic circuit and layout Apr 18, 2010 Issued
Array ( [id] => 6337770 [patent_doc_number] => 20100199107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/758640 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6531 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199107.pdf [firstpage_image] =>[orig_patent_app_number] => 12758640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758640
Secure exchange of information in electronic design automation Apr 11, 2010 Issued
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