Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6338595 [patent_doc_number] => 20100199239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SIMULATION METHOD AND SIMULATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/753832 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 15949 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199239.pdf [firstpage_image] =>[orig_patent_app_number] => 12753832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753832
SIMULATION METHOD AND SIMULATION PROGRAM Apr 1, 2010 Abandoned
Array ( [id] => 8220426 [patent_doc_number] => 08196081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-05 [patent_title] => 'Incremental placement and routing' [patent_app_type] => utility [patent_app_number] => 12/751175 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196081.pdf [firstpage_image] =>[orig_patent_app_number] => 12751175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751175
Incremental placement and routing Mar 30, 2010 Issued
Array ( [id] => 6410547 [patent_doc_number] => 20100180247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'AWARE MANUFACTURING OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/731118 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8274 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180247.pdf [firstpage_image] =>[orig_patent_app_number] => 12731118 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731118
Aware manufacturing of integrated circuits Mar 23, 2010 Issued
Array ( [id] => 6234634 [patent_doc_number] => 20100185997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS' [patent_app_type] => utility [patent_app_number] => 12/726413 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11737 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185997.pdf [firstpage_image] =>[orig_patent_app_number] => 12726413 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726413
Technology migration for integrated circuits with radical design restrictions Mar 17, 2010 Issued
Array ( [id] => 7694779 [patent_doc_number] => 20110231811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/724955 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9916 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20110231811.pdf [firstpage_image] =>[orig_patent_app_number] => 12724955 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724955
Modeling of cell delay change for electronic design automation Mar 15, 2010 Issued
Array ( [id] => 9023635 [patent_doc_number] => 08533634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product' [patent_app_type] => utility [patent_app_number] => 12/659396 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5612 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659396
Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product Mar 7, 2010 Issued
Array ( [id] => 6094140 [patent_doc_number] => 20110219277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'System and Method of Test Mode Gate Operation' [patent_app_type] => utility [patent_app_number] => 12/716565 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10696 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219277.pdf [firstpage_image] =>[orig_patent_app_number] => 12716565 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716565
System and method of test mode gate operation Mar 2, 2010 Issued
Array ( [id] => 8633014 [patent_doc_number] => 08365113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/708530 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 13202 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708530 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708530
Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs Feb 17, 2010 Issued
Array ( [id] => 6332799 [patent_doc_number] => 20100115481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Shape-Based Geometry Engine To Perform Smoothing And Other Layout Beautification Operations' [patent_app_type] => utility [patent_app_number] => 12/687080 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7877 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115481.pdf [firstpage_image] =>[orig_patent_app_number] => 12687080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687080
Shape-based geometry engine to perform smoothing and other layout beautification operations Jan 12, 2010 Issued
Array ( [id] => 8319810 [patent_doc_number] => 08234600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Computer readable storage medium storing program for generating reticle data, and method of generating reticle data' [patent_app_type] => utility [patent_app_number] => 12/684675 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 43 [patent_no_of_words] => 12038 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12684675 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684675
Computer readable storage medium storing program for generating reticle data, and method of generating reticle data Jan 7, 2010 Issued
Array ( [id] => 6099752 [patent_doc_number] => 20110163801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'Methods and Circuits for Optimizing Performance and Power Consumption in a Design and Circuit Employing Lower Threshold Voltage (LVT) Devices' [patent_app_type] => utility [patent_app_number] => 12/683075 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8858 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163801.pdf [firstpage_image] =>[orig_patent_app_number] => 12683075 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/683075
Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices Jan 5, 2010 Issued
Array ( [id] => 6153498 [patent_doc_number] => 20110156148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES' [patent_app_type] => utility [patent_app_number] => 12/649875 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156148.pdf [firstpage_image] =>[orig_patent_app_number] => 12649875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649875
Semiconductor device and method for making the same using semiconductor fin density design rules Dec 29, 2009 Issued
Array ( [id] => 8355148 [patent_doc_number] => 08250497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Method for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the same' [patent_app_type] => utility [patent_app_number] => 12/648895 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2842 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648895
Method for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the same Dec 28, 2009 Issued
Array ( [id] => 9012607 [patent_doc_number] => 08527928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Optimizing circuit layouts by configuring rooms for placing devices' [patent_app_type] => utility [patent_app_number] => 12/655092 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12655092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655092
Optimizing circuit layouts by configuring rooms for placing devices Dec 22, 2009 Issued
Array ( [id] => 9352465 [patent_doc_number] => 08671369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Quantum Karnaugh map' [patent_app_type] => utility [patent_app_number] => 12/633575 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7060 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12633575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/633575
Quantum Karnaugh map Dec 7, 2009 Issued
Array ( [id] => 8355156 [patent_doc_number] => 08250505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-21 [patent_title] => 'Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches' [patent_app_type] => utility [patent_app_number] => 12/592960 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6376 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12592960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/592960
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Dec 3, 2009 Issued
Array ( [id] => 8109601 [patent_doc_number] => 08156459 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-10 [patent_title] => 'Detecting differences between high level block diagram models' [patent_app_type] => utility [patent_app_number] => 12/615415 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4844 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156459.pdf [firstpage_image] =>[orig_patent_app_number] => 12615415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615415
Detecting differences between high level block diagram models Nov 9, 2009 Issued
Array ( [id] => 7683915 [patent_doc_number] => 20100122226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'LAYOUT DENSITY VERIFICATION SYSTEM AND LAYOUT DENSITY VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/612955 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3551 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122226.pdf [firstpage_image] =>[orig_patent_app_number] => 12612955 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612955
LAYOUT DENSITY VERIFICATION SYSTEM AND LAYOUT DENSITY VERIFICATION METHOD Nov 4, 2009 Abandoned
Array ( [id] => 8805023 [patent_doc_number] => 08443307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Methods and system for model-based generic matching and tuning' [patent_app_type] => utility [patent_app_number] => 12/613285 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9063 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12613285 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613285
Methods and system for model-based generic matching and tuning Nov 4, 2009 Issued
Array ( [id] => 6513088 [patent_doc_number] => 20100095258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Wiring layout method of integrated circuit and computer-readable medium storing a program executed by a computer to execute the same' [patent_app_type] => utility [patent_app_number] => 12/588995 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4703 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095258.pdf [firstpage_image] =>[orig_patent_app_number] => 12588995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588995
Wiring layout decision method of integrated circuit Nov 3, 2009 Issued
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