
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5949390
[patent_doc_number] => 20110107293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-05
[patent_title] => 'SIMULATION-BASED DESIGN STATE SNAPSHOTTING IN ELECTRONIC DESIGN AUTOMATION'
[patent_app_type] => utility
[patent_app_number] => 12/608645
[patent_app_country] => US
[patent_app_date] => 2009-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4628
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20110107293.pdf
[firstpage_image] =>[orig_patent_app_number] => 12608645
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/608645 | Simulation-based design state snapshotting in electronic design automation | Oct 28, 2009 | Issued |
Array
(
[id] => 9611801
[patent_doc_number] => 08788990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-22
[patent_title] => 'Reuse of circuit labels in subcircuit recognition'
[patent_app_type] => utility
[patent_app_number] => 12/604368
[patent_app_country] => US
[patent_app_date] => 2009-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 9176
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12604368
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/604368 | Reuse of circuit labels in subcircuit recognition | Oct 21, 2009 | Issued |
Array
(
[id] => 6263516
[patent_doc_number] => 20100031225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'Methods and systems for pattern generation based on multiple forms of design data'
[patent_app_type] => utility
[patent_app_number] => 12/588065
[patent_app_country] => US
[patent_app_date] => 2009-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5483
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20100031225.pdf
[firstpage_image] =>[orig_patent_app_number] => 12588065
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/588065 | Methods and systems for pattern generation based on multiple forms of design data | Oct 1, 2009 | Abandoned |
Array
(
[id] => 8331719
[patent_doc_number] => 08239794
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'System and method for estimating leakage current of an electronic circuit'
[patent_app_type] => utility
[patent_app_number] => 12/568985
[patent_app_country] => US
[patent_app_date] => 2009-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 13233
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568985
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/568985 | System and method for estimating leakage current of an electronic circuit | Sep 28, 2009 | Issued |
Array
(
[id] => 6621597
[patent_doc_number] => 20100064267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'Semiconductor device design support apparatus and substrate netlist generation method'
[patent_app_type] => utility
[patent_app_number] => 12/585115
[patent_app_country] => US
[patent_app_date] => 2009-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5209
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20100064267.pdf
[firstpage_image] =>[orig_patent_app_number] => 12585115
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/585115 | Semiconductor device design support apparatus and substrate netlist generation method | Sep 2, 2009 | Issued |
Array
(
[id] => 8536230
[patent_doc_number] => 08312397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-13
[patent_title] => 'Method for generating layout pattern of semiconductor device and layout pattern generating apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/585085
[patent_app_country] => US
[patent_app_date] => 2009-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4813
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12585085
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/585085 | Method for generating layout pattern of semiconductor device and layout pattern generating apparatus | Sep 1, 2009 | Issued |
Array
(
[id] => 9444364
[patent_doc_number] => 08713500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-29
[patent_title] => 'Computer program and apparatus for evaluating signal propagation delays'
[patent_app_type] => utility
[patent_app_number] => 12/552015
[patent_app_country] => US
[patent_app_date] => 2009-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 10870
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12552015
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/552015 | Computer program and apparatus for evaluating signal propagation delays | Aug 31, 2009 | Issued |
Array
(
[id] => 6246952
[patent_doc_number] => 20100136488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'PATTERN CREATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/548085
[patent_app_country] => US
[patent_app_date] => 2009-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4835
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20100136488.pdf
[firstpage_image] =>[orig_patent_app_number] => 12548085
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/548085 | PATTERN CREATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM | Aug 25, 2009 | Abandoned |
Array
(
[id] => 8235669
[patent_doc_number] => 08201129
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-12
[patent_title] => 'PLD architecture for flexible placement of IP function blocks'
[patent_app_type] => utility
[patent_app_number] => 12/465464
[patent_app_country] => US
[patent_app_date] => 2009-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3686
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/201/08201129.pdf
[firstpage_image] =>[orig_patent_app_number] => 12465464
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/465464 | PLD architecture for flexible placement of IP function blocks | May 12, 2009 | Issued |
Array
(
[id] => 8120447
[patent_doc_number] => 08161447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-17
[patent_title] => 'Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage'
[patent_app_type] => utility
[patent_app_number] => 12/463509
[patent_app_country] => US
[patent_app_date] => 2009-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/161/08161447.pdf
[firstpage_image] =>[orig_patent_app_number] => 12463509
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/463509 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | May 10, 2009 | Issued |
Array
(
[id] => 6281503
[patent_doc_number] => 20100257495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => '3D-IC Verification Method'
[patent_app_type] => utility
[patent_app_number] => 12/419255
[patent_app_country] => US
[patent_app_date] => 2009-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2404
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20100257495.pdf
[firstpage_image] =>[orig_patent_app_number] => 12419255
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/419255 | 3D-IC Verification Method | Apr 5, 2009 | Abandoned |
Array
(
[id] => 10873397
[patent_doc_number] => 08898618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'Interactive simplification of schematic diagram of integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 12/412045
[patent_app_country] => US
[patent_app_date] => 2009-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 27
[patent_no_of_words] => 6880
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12412045
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/412045 | Interactive simplification of schematic diagram of integrated circuit design | Mar 25, 2009 | Issued |
Array
(
[id] => 5476099
[patent_doc_number] => 20090249265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'PRINTED CIRCUIT BOARD DESIGNING APPARATUS AND PRINTED CIRCUIT BOARD DESIGNING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/409995
[patent_app_country] => US
[patent_app_date] => 2009-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3175
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249265.pdf
[firstpage_image] =>[orig_patent_app_number] => 12409995
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/409995 | PRINTED CIRCUIT BOARD DESIGNING APPARATUS AND PRINTED CIRCUIT BOARD DESIGNING METHOD | Mar 23, 2009 | Abandoned |
Array
(
[id] => 5459750
[patent_doc_number] => 20090259902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-15
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/382675
[patent_app_country] => US
[patent_app_date] => 2009-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3676
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20090259902.pdf
[firstpage_image] =>[orig_patent_app_number] => 12382675
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/382675 | Semiconductor device | Mar 19, 2009 | Issued |
Array
(
[id] => 5405771
[patent_doc_number] => 20090241086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-24
[patent_title] => 'METHOD OF MAKING PATTERN DATA, AND MEDIUM FOR STORING THE PROGRAM FOR MAKING THE PATTERN DATA'
[patent_app_type] => utility
[patent_app_number] => 12/405265
[patent_app_country] => US
[patent_app_date] => 2009-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8340
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20090241086.pdf
[firstpage_image] =>[orig_patent_app_number] => 12405265
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/405265 | Method of making pattern data, and medium for storing the program for making the pattern data | Mar 16, 2009 | Issued |
Array
(
[id] => 8235675
[patent_doc_number] => 08201137
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-06-12
[patent_title] => 'Method and apparatus for AMS simulation of integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 12/399855
[patent_app_country] => US
[patent_app_date] => 2009-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 31
[patent_no_of_words] => 11574
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/201/08201137.pdf
[firstpage_image] =>[orig_patent_app_number] => 12399855
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/399855 | Method and apparatus for AMS simulation of integrated circuit design | Mar 5, 2009 | Issued |
Array
(
[id] => 8120425
[patent_doc_number] => 08161434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-17
[patent_title] => 'Statistical formal activity analysis with consideration of temporal and spatial correlations'
[patent_app_type] => utility
[patent_app_number] => 12/399795
[patent_app_country] => US
[patent_app_date] => 2009-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 30
[patent_no_of_words] => 12936
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/161/08161434.pdf
[firstpage_image] =>[orig_patent_app_number] => 12399795
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/399795 | Statistical formal activity analysis with consideration of temporal and spatial correlations | Mar 5, 2009 | Issued |
Array
(
[id] => 6652389
[patent_doc_number] => 20100229131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION'
[patent_app_type] => utility
[patent_app_number] => 12/398535
[patent_app_country] => US
[patent_app_date] => 2009-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2268
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20100229131.pdf
[firstpage_image] =>[orig_patent_app_number] => 12398535
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/398535 | Swarm intelligence for electrical design space modeling and optimization | Mar 4, 2009 | Issued |
Array
(
[id] => 5387609
[patent_doc_number] => 20090228854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'Wiring model library constructing device and constructing method, and layout parameter extracting device and extracting method'
[patent_app_type] => utility
[patent_app_number] => 12/379765
[patent_app_country] => US
[patent_app_date] => 2009-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 18169
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20090228854.pdf
[firstpage_image] =>[orig_patent_app_number] => 12379765
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/379765 | Wiring model library constructing device and constructing method, and layout parameter extracting device and extracting method | Feb 26, 2009 | Abandoned |
Array
(
[id] => 6535348
[patent_doc_number] => 20100218155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-26
[patent_title] => 'Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design'
[patent_app_type] => utility
[patent_app_number] => 12/394035
[patent_app_country] => US
[patent_app_date] => 2009-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3697
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20100218155.pdf
[firstpage_image] =>[orig_patent_app_number] => 12394035
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/394035 | Automated critical area allocation in a physical synthesized hierarchical design | Feb 25, 2009 | Issued |