Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5533399 [patent_doc_number] => 20090233187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Designing method of photo-mask and method of manufacturing semiconductor device using the photo-mask' [patent_app_type] => utility [patent_app_number] => 12/379705 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3858 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20090233187.pdf [firstpage_image] =>[orig_patent_app_number] => 12379705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379705
Designing method of photo-mask and method of manufacturing semiconductor device using the photo-mask Feb 25, 2009 Issued
Array ( [id] => 5438026 [patent_doc_number] => 20090172613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Mutual Inductance extraction using dipole approximations' [patent_app_type] => utility [patent_app_number] => 12/380138 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16335 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172613.pdf [firstpage_image] =>[orig_patent_app_number] => 12380138 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/380138
Mutual inductance extraction using dipole approximations Feb 22, 2009 Issued
Array ( [id] => 8208348 [patent_doc_number] => 08191016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'System and method for compressed post-OPC data' [patent_app_type] => utility [patent_app_number] => 12/391185 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6812 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/191/08191016.pdf [firstpage_image] =>[orig_patent_app_number] => 12391185 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/391185
System and method for compressed post-OPC data Feb 22, 2009 Issued
Array ( [id] => 8412697 [patent_doc_number] => 08276109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Mixed-height high speed reduced area cell library' [patent_app_type] => utility [patent_app_number] => 12/370065 [patent_app_country] => US [patent_app_date] => 2009-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7772 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12370065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/370065
Mixed-height high speed reduced area cell library Feb 11, 2009 Issued
Array ( [id] => 7706542 [patent_doc_number] => 08091060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-03 [patent_title] => 'Clock domain partitioning of programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/368435 [patent_app_country] => US [patent_app_date] => 2009-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7353 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091060.pdf [firstpage_image] =>[orig_patent_app_number] => 12368435 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/368435
Clock domain partitioning of programmable integrated circuits Feb 9, 2009 Issued
Array ( [id] => 6338570 [patent_doc_number] => 20100199236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING RLC MODELING AND EXTRACTION FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D-IC) DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/363485 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7658 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199236.pdf [firstpage_image] =>[orig_patent_app_number] => 12363485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363485
Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs Jan 29, 2009 Issued
Array ( [id] => 6338652 [patent_doc_number] => 20100199247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Communicating configuration information across a programmable analog tile to another tile' [patent_app_type] => utility [patent_app_number] => 12/322375 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11889 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199247.pdf [firstpage_image] =>[orig_patent_app_number] => 12322375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/322375
Communicating configuration information across a programmable analog tile to another tile Jan 29, 2009 Issued
Array ( [id] => 8837325 [patent_doc_number] => 08453094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Enforcement of semiconductor structure regularity for localized transistors and interconnect' [patent_app_type] => utility [patent_app_number] => 12/363705 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10283 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12363705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363705
Enforcement of semiconductor structure regularity for localized transistors and interconnect Jan 29, 2009 Issued
Array ( [id] => 8208364 [patent_doc_number] => 08191021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Single event transient mitigation and measurement in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/361955 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 18606 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/191/08191021.pdf [firstpage_image] =>[orig_patent_app_number] => 12361955 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361955
Single event transient mitigation and measurement in integrated circuits Jan 28, 2009 Issued
Array ( [id] => 9665991 [patent_doc_number] => 08813001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'System and method for efficient and optimal minimum area retiming' [patent_app_type] => utility [patent_app_number] => 12/361845 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5851 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12361845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361845
System and method for efficient and optimal minimum area retiming Jan 28, 2009 Issued
Array ( [id] => 8001379 [patent_doc_number] => 08082537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Method and apparatus for implementing spatially programmable through die vias in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/361115 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082537.pdf [firstpage_image] =>[orig_patent_app_number] => 12361115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361115
Method and apparatus for implementing spatially programmable through die vias in an integrated circuit Jan 27, 2009 Issued
Array ( [id] => 5516916 [patent_doc_number] => 20090217223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Layout design method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/320325 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5088 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217223.pdf [firstpage_image] =>[orig_patent_app_number] => 12320325 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/320325
Layout design method of semiconductor integrated circuit Jan 22, 2009 Issued
Array ( [id] => 5553979 [patent_doc_number] => 20090287965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'VERIFICATION SUPPORTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/359105 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20090287965.pdf [firstpage_image] =>[orig_patent_app_number] => 12359105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359105
Verification supporting system Jan 22, 2009 Issued
Array ( [id] => 6225373 [patent_doc_number] => 20100181847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'METHOD FOR REDUCING SUPPLY VOLTAGE DROP IN DIGITAL CIRCUIT BLOCK AND RELATED LAYOUT ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/358215 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3707 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20100181847.pdf [firstpage_image] =>[orig_patent_app_number] => 12358215 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/358215
METHOD FOR REDUCING SUPPLY VOLTAGE DROP IN DIGITAL CIRCUIT BLOCK AND RELATED LAYOUT ARCHITECTURE Jan 21, 2009 Abandoned
Array ( [id] => 5353389 [patent_doc_number] => 20090184733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL' [patent_app_type] => utility [patent_app_number] => 12/354655 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5012 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184733.pdf [firstpage_image] =>[orig_patent_app_number] => 12354655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354655
LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL Jan 14, 2009 Abandoned
Array ( [id] => 8775597 [patent_doc_number] => 08429573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Data generation method for semiconductor device, and electron beam exposure system' [patent_app_type] => utility [patent_app_number] => 12/350525 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10091 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12350525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350525
Data generation method for semiconductor device, and electron beam exposure system Jan 7, 2009 Issued
Array ( [id] => 4621760 [patent_doc_number] => 08001491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Organic thin film transistor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/344255 [patent_app_country] => US [patent_app_date] => 2008-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001491.pdf [firstpage_image] =>[orig_patent_app_number] => 12344255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344255
Organic thin film transistor and method of fabricating the same Dec 24, 2008 Issued
Array ( [id] => 9358738 [patent_doc_number] => 08677293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Feasibility of IC edits' [patent_app_type] => utility [patent_app_number] => 12/341505 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3654 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12341505 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341505
Feasibility of IC edits Dec 21, 2008 Issued
Array ( [id] => 5438023 [patent_doc_number] => 20090172610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'System and method for circuit simulation' [patent_app_type] => utility [patent_app_number] => 12/314825 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172610.pdf [firstpage_image] =>[orig_patent_app_number] => 12314825 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314825
System and method for circuit simulation Dec 16, 2008 Issued
Array ( [id] => 5486975 [patent_doc_number] => 20090276740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/335105 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 9127 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276740.pdf [firstpage_image] =>[orig_patent_app_number] => 12335105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/335105
Verification supporting apparatus, verification supporting method, and computer product Dec 14, 2008 Issued
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