Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7756694 [patent_doc_number] => 08112726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Phase-shifting masks with sub-wavelength diffractive optical elements' [patent_app_type] => utility [patent_app_number] => 12/316064 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112726.pdf [firstpage_image] =>[orig_patent_app_number] => 12316064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/316064
Phase-shifting masks with sub-wavelength diffractive optical elements Dec 8, 2008 Issued
Array ( [id] => 5286725 [patent_doc_number] => 20090100400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Phase-shifting masks with sub-wavelength diffractive optical elements' [patent_app_type] => utility [patent_app_number] => 12/316085 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100400.pdf [firstpage_image] =>[orig_patent_app_number] => 12316085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/316085
Phase-shifting masks with sub-wavelength diffractive optical elements Dec 8, 2008 Issued
Array ( [id] => 7756707 [patent_doc_number] => 08112733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Method and apparatus for routing with independent goals on different layers' [patent_app_type] => utility [patent_app_number] => 12/326100 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 16593 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112733.pdf [firstpage_image] =>[orig_patent_app_number] => 12326100 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/326100
Method and apparatus for routing with independent goals on different layers Nov 30, 2008 Issued
Array ( [id] => 5332887 [patent_doc_number] => 20090113364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION' [patent_app_type] => utility [patent_app_number] => 12/325774 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113364.pdf [firstpage_image] =>[orig_patent_app_number] => 12325774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/325774
Apparatus and computer program product for semiconductor yield estimation Nov 30, 2008 Issued
Array ( [id] => 9458737 [patent_doc_number] => 08719764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Generalized constraint collection management method' [patent_app_type] => utility [patent_app_number] => 12/323118 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11901 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12323118 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323118
Generalized constraint collection management method Nov 24, 2008 Issued
Array ( [id] => 5273737 [patent_doc_number] => 20090077513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 12/323042 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11902 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077513.pdf [firstpage_image] =>[orig_patent_app_number] => 12323042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323042
Generalized constraint collection management method Nov 24, 2008 Issued
Array ( [id] => 7803853 [patent_doc_number] => 08132137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-06 [patent_title] => 'Prediction of dynamic current waveform and spectrum in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/268365 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4942 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132137.pdf [firstpage_image] =>[orig_patent_app_number] => 12268365 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268365
Prediction of dynamic current waveform and spectrum in a semiconductor device Nov 9, 2008 Issued
Array ( [id] => 5262818 [patent_doc_number] => 20090115503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Variability-Aware Scheme for High-Performance Asynchronous Circuit Voltage Reglulation' [patent_app_type] => utility [patent_app_number] => 12/265585 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 22592 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115503.pdf [firstpage_image] =>[orig_patent_app_number] => 12265585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265585
Variability-aware scheme for high-performance asynchronous circuit voltage regulation Nov 4, 2008 Issued
Array ( [id] => 7756704 [patent_doc_number] => 08112732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'System and computer program product for diffusion based cell placement migration' [patent_app_type] => utility [patent_app_number] => 12/264619 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5084 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112732.pdf [firstpage_image] =>[orig_patent_app_number] => 12264619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264619
System and computer program product for diffusion based cell placement migration Nov 3, 2008 Issued
Array ( [id] => 7706541 [patent_doc_number] => 08091059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Method for diffusion based cell placement migration' [patent_app_type] => utility [patent_app_number] => 12/264583 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5088 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091059.pdf [firstpage_image] =>[orig_patent_app_number] => 12264583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264583
Method for diffusion based cell placement migration Nov 3, 2008 Issued
Array ( [id] => 5587508 [patent_doc_number] => 20090106710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'METHOD AND APPARATUS FOR SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/258403 [patent_app_country] => US [patent_app_date] => 2008-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 25493 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106710.pdf [firstpage_image] =>[orig_patent_app_number] => 12258403 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/258403
Method and apparatus for pre-tabulating sub-networks Oct 24, 2008 Issued
Array ( [id] => 7718800 [patent_doc_number] => 08095897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Methods and systems for layout and routing using alternating aperture phase shift masks' [patent_app_type] => utility [patent_app_number] => 12/256108 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6936 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095897.pdf [firstpage_image] =>[orig_patent_app_number] => 12256108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/256108
Methods and systems for layout and routing using alternating aperture phase shift masks Oct 21, 2008 Issued
Array ( [id] => 4621780 [patent_doc_number] => 08001511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies' [patent_app_type] => utility [patent_app_number] => 12/245858 [patent_app_country] => US [patent_app_date] => 2008-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 14172 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001511.pdf [firstpage_image] =>[orig_patent_app_number] => 12245858 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/245858
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies Oct 5, 2008 Issued
Array ( [id] => 4621779 [patent_doc_number] => 08001510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Automated method of architecture mapping selection from constrained high level language description via element characterization' [patent_app_type] => utility [patent_app_number] => 12/205825 [patent_app_country] => US [patent_app_date] => 2008-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7344 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001510.pdf [firstpage_image] =>[orig_patent_app_number] => 12205825 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/205825
Automated method of architecture mapping selection from constrained high level language description via element characterization Sep 4, 2008 Issued
Array ( [id] => 5454680 [patent_doc_number] => 20090070717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Method and System for Generating Coverage Data for a Switch Frequency of HDL or VHDL Signals' [patent_app_type] => utility [patent_app_number] => 12/205476 [patent_app_country] => US [patent_app_date] => 2008-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1621 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070717.pdf [firstpage_image] =>[orig_patent_app_number] => 12205476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/205476
Generating coverage data for a switch frequency of HDL or VHDL signals Sep 4, 2008 Issued
Array ( [id] => 5351687 [patent_doc_number] => 20090007048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR' [patent_app_type] => utility [patent_app_number] => 12/203335 [patent_app_country] => US [patent_app_date] => 2008-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007048.pdf [firstpage_image] =>[orig_patent_app_number] => 12203335 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203335
DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR Sep 2, 2008 Abandoned
Array ( [id] => 9049396 [patent_doc_number] => 08543954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/203115 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 40 [patent_no_of_words] => 19096 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12203115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203115
Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs Sep 1, 2008 Issued
Array ( [id] => 9049396 [patent_doc_number] => 08543954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/203115 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 40 [patent_no_of_words] => 19096 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12203115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203115
Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs Sep 1, 2008 Issued
Array ( [id] => 9169976 [patent_doc_number] => 08595669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-26 [patent_title] => 'Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/203128 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 48 [patent_no_of_words] => 20856 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12203128 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203128
Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs Sep 1, 2008 Issued
Array ( [id] => 7780234 [patent_doc_number] => 08122395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'On chip timing adjustment in multi-channel fast data transfer' [patent_app_type] => utility [patent_app_number] => 12/194570 [patent_app_country] => US [patent_app_date] => 2008-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5529 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122395.pdf [firstpage_image] =>[orig_patent_app_number] => 12194570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/194570
On chip timing adjustment in multi-channel fast data transfer Aug 19, 2008 Issued
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