Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7993383 [patent_doc_number] => 08079000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method and apparatus for performing formal verification using data-flow graphs' [patent_app_type] => utility [patent_app_number] => 12/188978 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 108 [patent_no_of_words] => 41504 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/079/08079000.pdf [firstpage_image] =>[orig_patent_app_number] => 12188978 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/188978
Method and apparatus for performing formal verification using data-flow graphs Aug 7, 2008 Issued
Array ( [id] => 5413633 [patent_doc_number] => 20090039520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'SEMICONDUCTOR CIRCUIT DEVICE, WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/188465 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11864 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20090039520.pdf [firstpage_image] =>[orig_patent_app_number] => 12188465 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/188465
SEMICONDUCTOR CIRCUIT DEVICE, WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE AND DATA PROCESSING SYSTEM Aug 7, 2008 Abandoned
Array ( [id] => 4793306 [patent_doc_number] => 20080294280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'PROCESSING CONDITION DETERMINING METHOD AND APPARATUS, DISPLAY METHOD AND APPARATUS, PROCESSING APPARATUS, MEASUREMENT APPARATUS AND EXPOSURE APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND PROGRAM AND INFORMATION RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/181705 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16033 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294280.pdf [firstpage_image] =>[orig_patent_app_number] => 12181705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181705
Processing condition determining method and apparatus, display method and apparatus, processing apparatus, measurement apparatus and exposure apparatus, substrate processing system, and program and information recording medium Jul 28, 2008 Issued
Array ( [id] => 49072 [patent_doc_number] => 07779378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Computer program product for extending incremental verification of circuit design to encompass verification restraints' [patent_app_type] => utility [patent_app_number] => 12/180533 [patent_app_country] => US [patent_app_date] => 2008-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5771 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779378.pdf [firstpage_image] =>[orig_patent_app_number] => 12180533 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180533
Computer program product for extending incremental verification of circuit design to encompass verification restraints Jul 25, 2008 Issued
Array ( [id] => 4780904 [patent_doc_number] => 20080288903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Generating testcases based on numbers of testcases previously generated' [patent_app_type] => utility [patent_app_number] => 12/220497 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288903.pdf [firstpage_image] =>[orig_patent_app_number] => 12220497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/220497
Generating testcases based on numbers of testcases previously generated Jul 23, 2008 Issued
Array ( [id] => 9486672 [patent_doc_number] => 08732635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Apparatus and methods for power management in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/165665 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12165665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165665
Apparatus and methods for power management in integrated circuits Jun 30, 2008 Issued
Array ( [id] => 5312125 [patent_doc_number] => 20090019406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'VERIFICATION APPARATUS AND VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/163486 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019406.pdf [firstpage_image] =>[orig_patent_app_number] => 12163486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163486
Verification apparatus and verification method Jun 26, 2008 Issued
Array ( [id] => 4761354 [patent_doc_number] => 20080313580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Methodology for Hierarchy Separation at Asynchronous Clock Domain Boundaries for Multi-Voltage Optimization Using Design Compiler' [patent_app_type] => utility [patent_app_number] => 12/137835 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3081 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313580.pdf [firstpage_image] =>[orig_patent_app_number] => 12137835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137835
Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler Jun 11, 2008 Issued
Array ( [id] => 7768473 [patent_doc_number] => 08117584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Method of implementing low ESL and controlled ESR of multilayer capacitor' [patent_app_type] => utility [patent_app_number] => 12/155805 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 60 [patent_no_of_words] => 7811 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117584.pdf [firstpage_image] =>[orig_patent_app_number] => 12155805 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155805
Method of implementing low ESL and controlled ESR of multilayer capacitor Jun 9, 2008 Issued
Array ( [id] => 4951245 [patent_doc_number] => 20080307371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Manufacturing Aware Design and Design Aware Manufacturing' [patent_app_type] => utility [patent_app_number] => 12/136044 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11158 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307371.pdf [firstpage_image] =>[orig_patent_app_number] => 12136044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136044
Manufacturing aware design and design aware manufacturing of an integrated circuit Jun 8, 2008 Issued
Array ( [id] => 4540927 [patent_doc_number] => 07954075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Vector sequence simplification for circuit verification' [patent_app_type] => utility [patent_app_number] => 12/134875 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6289 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/954/07954075.pdf [firstpage_image] =>[orig_patent_app_number] => 12134875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134875
Vector sequence simplification for circuit verification Jun 5, 2008 Issued
Array ( [id] => 7972385 [patent_doc_number] => 07941771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method for functional verification of an integrated circuit model for constituting a verification platform, equipment emulator and verification platform' [patent_app_type] => utility [patent_app_number] => 12/133085 [patent_app_country] => US [patent_app_date] => 2008-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10565 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941771.pdf [firstpage_image] =>[orig_patent_app_number] => 12133085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133085
Method for functional verification of an integrated circuit model for constituting a verification platform, equipment emulator and verification platform Jun 3, 2008 Issued
Array ( [id] => 7495213 [patent_doc_number] => 08032850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Structure for an absolute duty cycle measurement circuit' [patent_app_type] => utility [patent_app_number] => 12/129945 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9394 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032850.pdf [firstpage_image] =>[orig_patent_app_number] => 12129945 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129945
Structure for an absolute duty cycle measurement circuit May 29, 2008 Issued
Array ( [id] => 4632013 [patent_doc_number] => 08010923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-30 [patent_title] => 'Latch based optimization during implementation of circuit designs for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/128335 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6094 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010923.pdf [firstpage_image] =>[orig_patent_app_number] => 12128335 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128335
Latch based optimization during implementation of circuit designs for programmable logic devices May 27, 2008 Issued
Array ( [id] => 5430409 [patent_doc_number] => 20090089719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Structure for a Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit' [patent_app_type] => utility [patent_app_number] => 12/127245 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4400 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089719.pdf [firstpage_image] =>[orig_patent_app_number] => 12127245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127245
Structure for a stacked power clamp having a BigFET gate pull-up circuit May 26, 2008 Issued
Array ( [id] => 4511518 [patent_doc_number] => 07949976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Systematic approach for performing cell replacement in a circuit to meet timing requirements' [patent_app_type] => utility [patent_app_number] => 12/125945 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9358 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949976.pdf [firstpage_image] =>[orig_patent_app_number] => 12125945 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125945
Systematic approach for performing cell replacement in a circuit to meet timing requirements May 22, 2008 Issued
Array ( [id] => 7525097 [patent_doc_number] => 08028267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Pattern designing method, pattern designing program and pattern designing apparatus' [patent_app_type] => utility [patent_app_number] => 12/124435 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9046 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028267.pdf [firstpage_image] =>[orig_patent_app_number] => 12124435 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124435
Pattern designing method, pattern designing program and pattern designing apparatus May 20, 2008 Issued
Array ( [id] => 4621770 [patent_doc_number] => 08001501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Method for circuit design' [patent_app_type] => utility [patent_app_number] => 12/122785 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4054 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001501.pdf [firstpage_image] =>[orig_patent_app_number] => 12122785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122785
Method for circuit design May 18, 2008 Issued
Array ( [id] => 5554071 [patent_doc_number] => 20090288057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'System and Method for Ordering the Selection of Integrated Circuit Chips' [patent_app_type] => utility [patent_app_number] => 12/120695 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20090288057.pdf [firstpage_image] =>[orig_patent_app_number] => 12120695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/120695
System and Method for Ordering the Selection of Integrated Circuit Chips May 14, 2008 Abandoned
Array ( [id] => 5273730 [patent_doc_number] => 20090077506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Simultaneous Multi-Layer Fill Generation' [patent_app_type] => utility [patent_app_number] => 12/121135 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12407 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077506.pdf [firstpage_image] =>[orig_patent_app_number] => 12121135 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121135
Simultaneous Multi-Layer Fill Generation May 14, 2008 Abandoned
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