Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16864905 [patent_doc_number] => 11023650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Apparatus and method for circuit timing fixing using extension metal sections and alternate vias [patent_app_type] => utility [patent_app_number] => 16/663332 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4991 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663332
Apparatus and method for circuit timing fixing using extension metal sections and alternate vias Oct 23, 2019 Issued
Array ( [id] => 16794993 [patent_doc_number] => 20210124810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => METHOD OF DEBUGGING HARDWARE AND FIRMWARE OF DATA STORAGE [patent_app_type] => utility [patent_app_number] => 16/662374 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662374
Method of debugging hardware and firmware of data storage Oct 23, 2019 Issued
Array ( [id] => 16545736 [patent_doc_number] => 20200412151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => POWER CONTROL CIRCUIT AND POWER CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/590388 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590388
Power control circuit and power control method Oct 1, 2019 Issued
Array ( [id] => 16880231 [patent_doc_number] => 11030381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Leakage analysis on semiconductor device [patent_app_type] => utility [patent_app_number] => 16/586658 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586658 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586658
Leakage analysis on semiconductor device Sep 26, 2019 Issued
Array ( [id] => 15654617 [patent_doc_number] => 20200089839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SYSTEM AND METHOD FOR ESTIMATION OF CHIP FLOORPLAN ACTIVITY [patent_app_type] => utility [patent_app_number] => 16/579836 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579836
System and method for estimation of chip floorplan activity Sep 23, 2019 Issued
Array ( [id] => 15352675 [patent_doc_number] => 20200014229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => INTELLIGENT SWITCH SYSTEM [patent_app_type] => utility [patent_app_number] => 16/574505 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574505
Intelligent switch system Sep 17, 2019 Issued
Array ( [id] => 15654599 [patent_doc_number] => 20200089830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Elmore Delay Time (EDT)-Based Resistance Model [patent_app_type] => utility [patent_app_number] => 16/568984 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568984
Elmore delay time (EDT)-based resistance model Sep 11, 2019 Issued
Array ( [id] => 16608294 [patent_doc_number] => 10909302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques [patent_app_type] => utility [patent_app_number] => 16/569575 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569575
Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques Sep 11, 2019 Issued
Array ( [id] => 17515898 [patent_doc_number] => 11295053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Dielet design techniques [patent_app_type] => utility [patent_app_number] => 16/569482 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569482 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569482
Dielet design techniques Sep 11, 2019 Issued
Array ( [id] => 16500891 [patent_doc_number] => 10866272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Simulation circuit and simulation method [patent_app_type] => utility [patent_app_number] => 16/557773 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5895 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557773
Simulation circuit and simulation method Aug 29, 2019 Issued
Array ( [id] => 17018757 [patent_doc_number] => 11088405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Battery pack temperature detection system [patent_app_type] => utility [patent_app_number] => 16/548987 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548987
Battery pack temperature detection system Aug 22, 2019 Issued
Array ( [id] => 15260981 [patent_doc_number] => 20190379224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => INTELLIGENT SWITCH SYSTEM [patent_app_type] => utility [patent_app_number] => 16/549170 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549170
Intelligent switch system Aug 22, 2019 Issued
Array ( [id] => 16431852 [patent_doc_number] => 10831938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Parallel power down processing of integrated circuit design [patent_app_type] => utility [patent_app_number] => 16/540094 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6463 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540094
Parallel power down processing of integrated circuit design Aug 13, 2019 Issued
Array ( [id] => 16346572 [patent_doc_number] => 20200311223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD FOR DETERMINING LAYOUT OF ELEMENT AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/540292 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540292 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540292
METHOD FOR DETERMINING LAYOUT OF ELEMENT AND DISPLAY DEVICE Aug 13, 2019 Abandoned
Array ( [id] => 18155223 [patent_doc_number] => 11568204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Optimization apparatus and control method thereof [patent_app_type] => utility [patent_app_number] => 16/524784 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10292 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524784
Optimization apparatus and control method thereof Jul 28, 2019 Issued
Array ( [id] => 16598834 [patent_doc_number] => 20210025365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => POWER SUPPLY DURING VEHICLE STARTUP [patent_app_type] => utility [patent_app_number] => 16/519025 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/519025
Power supply during vehicle startup Jul 22, 2019 Issued
Array ( [id] => 16957460 [patent_doc_number] => 11061317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Method of fabricating an integrated circuit with non-printable dummy features [patent_app_type] => utility [patent_app_number] => 16/517740 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517740
Method of fabricating an integrated circuit with non-printable dummy features Jul 21, 2019 Issued
Array ( [id] => 15370449 [patent_doc_number] => 20200020989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => METHOD FOR CHARGING SECONDARY BATTERY [patent_app_type] => utility [patent_app_number] => 16/443946 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443946
Method for charging secondary battery Jun 17, 2019 Issued
Array ( [id] => 15258209 [patent_doc_number] => 20190377838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Method and System for Designing a Distributed Heterogeneous Computing and Control System [patent_app_type] => utility [patent_app_number] => 16/431966 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431966 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431966
Method and system for designing a distributed heterogeneous computing and control system Jun 4, 2019 Issued
Array ( [id] => 14873087 [patent_doc_number] => 20190286785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT [patent_app_type] => utility [patent_app_number] => 16/432139 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432139
DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT Jun 4, 2019 Abandoned
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