Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4578074 [patent_doc_number] => 07823108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Chip having timing analysis of paths performed within the chip during the design process' [patent_app_type] => utility [patent_app_number] => 11/934995 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823108.pdf [firstpage_image] =>[orig_patent_app_number] => 11934995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934995
Chip having timing analysis of paths performed within the chip during the design process Nov 4, 2007 Issued
Array ( [id] => 4837156 [patent_doc_number] => 20080134131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Simulation model making method' [patent_app_type] => utility [patent_app_number] => 11/976025 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134131.pdf [firstpage_image] =>[orig_patent_app_number] => 11976025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976025
Simulation model making method Oct 18, 2007 Abandoned
Array ( [id] => 4895463 [patent_doc_number] => 20080104563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Timing verification method and timing verification apparatus' [patent_app_type] => utility [patent_app_number] => 11/907395 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10418 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104563.pdf [firstpage_image] =>[orig_patent_app_number] => 11907395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907395
Timing verification method and timing verification apparatus Oct 10, 2007 Issued
Array ( [id] => 4592940 [patent_doc_number] => 07853916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Methods of using one of a plurality of configuration bitstreams for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/974355 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 10623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853916.pdf [firstpage_image] =>[orig_patent_app_number] => 11974355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/974355
Methods of using one of a plurality of configuration bitstreams for an integrated circuit Oct 10, 2007 Issued
Array ( [id] => 6641259 [patent_doc_number] => 20100005438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'PROCESSING METHOD. PROCESSING EQUIPMENT, PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/440685 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 22538 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005438.pdf [firstpage_image] =>[orig_patent_app_number] => 12440685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/440685
Processing method of electric information in CAD system, processing device of electric information in CAD system, program and computer-readable storage medium Oct 9, 2007 Issued
Array ( [id] => 7518005 [patent_doc_number] => 08042087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Method to design network-on-chip (NOC)-based communication systems' [patent_app_type] => utility [patent_app_number] => 12/375525 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5692 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/042/08042087.pdf [firstpage_image] =>[orig_patent_app_number] => 12375525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/375525
Method to design network-on-chip (NOC)-based communication systems Oct 9, 2007 Issued
Array ( [id] => 4591311 [patent_doc_number] => 07827519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs' [patent_app_type] => utility [patent_app_number] => 11/866385 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827519.pdf [firstpage_image] =>[orig_patent_app_number] => 11866385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866385
Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs Oct 1, 2007 Issued
Array ( [id] => 5510481 [patent_doc_number] => 20090083688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/860775 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3963 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083688.pdf [firstpage_image] =>[orig_patent_app_number] => 11860775 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860775
Method and apparatus for generating a layout for a transistor Sep 24, 2007 Issued
Array ( [id] => 5510486 [patent_doc_number] => 20090083693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'FLASH-BASED UPDATING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 11/861195 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7643 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083693.pdf [firstpage_image] =>[orig_patent_app_number] => 11861195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861195
Flash-based updating techniques for high-accuracy high efficiency mask synthesis Sep 24, 2007 Issued
Array ( [id] => 5510483 [patent_doc_number] => 20090083690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/859965 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7951 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083690.pdf [firstpage_image] =>[orig_patent_app_number] => 11859965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/859965
SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT Sep 23, 2007 Abandoned
Array ( [id] => 4487544 [patent_doc_number] => 07870524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-11 [patent_title] => 'Method and system for automating unit performance testing in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/860475 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2937 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870524.pdf [firstpage_image] =>[orig_patent_app_number] => 11860475 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860475
Method and system for automating unit performance testing in integrated circuit design Sep 23, 2007 Issued
Array ( [id] => 4582506 [patent_doc_number] => 07840918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Method and apparatus for physical implementation of a power optimized circuit design' [patent_app_type] => utility [patent_app_number] => 11/903465 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7487 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840918.pdf [firstpage_image] =>[orig_patent_app_number] => 11903465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/903465
Method and apparatus for physical implementation of a power optimized circuit design Sep 20, 2007 Issued
Array ( [id] => 17615 [patent_doc_number] => 07805698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-28 [patent_title] => 'Methods and systems for physical hierarchy configuration engine and graphical editor' [patent_app_type] => utility [patent_app_number] => 11/857985 [patent_app_country] => US [patent_app_date] => 2007-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7685 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805698.pdf [firstpage_image] =>[orig_patent_app_number] => 11857985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/857985
Methods and systems for physical hierarchy configuration engine and graphical editor Sep 18, 2007 Issued
Array ( [id] => 8899592 [patent_doc_number] => 08479126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Parametric yield improvement flow incorporating sigma to target distance' [patent_app_type] => utility [patent_app_number] => 11/847126 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4532 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11847126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847126
Parametric yield improvement flow incorporating sigma to target distance Aug 28, 2007 Issued
Array ( [id] => 28588 [patent_doc_number] => 07797660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Semiconductor integrated circuit for controlling substrate bias' [patent_app_type] => utility [patent_app_number] => 11/892585 [patent_app_country] => US [patent_app_date] => 2007-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4744 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797660.pdf [firstpage_image] =>[orig_patent_app_number] => 11892585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892585
Semiconductor integrated circuit for controlling substrate bias Aug 23, 2007 Issued
Array ( [id] => 5448188 [patent_doc_number] => 20090049414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE' [patent_app_type] => utility [patent_app_number] => 11/840075 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6107 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20090049414.pdf [firstpage_image] =>[orig_patent_app_number] => 11840075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840075
METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE Aug 15, 2007 Abandoned
Array ( [id] => 69215 [patent_doc_number] => 07761828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Partitioning electronic circuit designs into simulation-ready blocks' [patent_app_type] => utility [patent_app_number] => 11/840175 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11961 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 806 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761828.pdf [firstpage_image] =>[orig_patent_app_number] => 11840175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840175
Partitioning electronic circuit designs into simulation-ready blocks Aug 15, 2007 Issued
Array ( [id] => 5087078 [patent_doc_number] => 20070277129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS' [patent_app_type] => utility [patent_app_number] => 11/837732 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11675 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277129.pdf [firstpage_image] =>[orig_patent_app_number] => 11837732 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/837732
Technology migration for integrated circuits with radical design restrictions Aug 12, 2007 Issued
Array ( [id] => 6535207 [patent_doc_number] => 20100218145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Multilayer finite difference methods for electrical modeling of packages and printed circuit boards' [patent_app_type] => utility [patent_app_number] => 11/888705 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218145.pdf [firstpage_image] =>[orig_patent_app_number] => 11888705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888705
Multilayer finite difference methods for electrical modeling of packages and printed circuit boards Aug 1, 2007 Issued
Array ( [id] => 4735678 [patent_doc_number] => 20080052660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'METHOD OF CORRECTING A DESIGNED PATTERN OF A MASK' [patent_app_type] => utility [patent_app_number] => 11/830265 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3513 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052660.pdf [firstpage_image] =>[orig_patent_app_number] => 11830265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830265
METHOD OF CORRECTING A DESIGNED PATTERN OF A MASK Jul 29, 2007 Abandoned
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