
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4578074
[patent_doc_number] => 07823108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-26
[patent_title] => 'Chip having timing analysis of paths performed within the chip during the design process'
[patent_app_type] => utility
[patent_app_number] => 11/934995
[patent_app_country] => US
[patent_app_date] => 2007-11-05
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/823/07823108.pdf
[firstpage_image] =>[orig_patent_app_number] => 11934995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934995 | Chip having timing analysis of paths performed within the chip during the design process | Nov 4, 2007 | Issued |
Array
(
[id] => 4837156
[patent_doc_number] => 20080134131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Simulation model making method'
[patent_app_type] => utility
[patent_app_number] => 11/976025
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[patent_app_date] => 2007-10-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0134/20080134131.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976025
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976025 | Simulation model making method | Oct 18, 2007 | Abandoned |
Array
(
[id] => 4895463
[patent_doc_number] => 20080104563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'Timing verification method and timing verification apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/907395
[patent_app_country] => US
[patent_app_date] => 2007-10-11
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[pdf_file] => publications/A1/0104/20080104563.pdf
[firstpage_image] =>[orig_patent_app_number] => 11907395
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907395 | Timing verification method and timing verification apparatus | Oct 10, 2007 | Issued |
Array
(
[id] => 4592940
[patent_doc_number] => 07853916
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-14
[patent_title] => 'Methods of using one of a plurality of configuration bitstreams for an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/974355
[patent_app_country] => US
[patent_app_date] => 2007-10-11
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[pdf_file] => patents/07/853/07853916.pdf
[firstpage_image] =>[orig_patent_app_number] => 11974355
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/974355 | Methods of using one of a plurality of configuration bitstreams for an integrated circuit | Oct 10, 2007 | Issued |
Array
(
[id] => 6641259
[patent_doc_number] => 20100005438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-07
[patent_title] => 'PROCESSING METHOD. PROCESSING EQUIPMENT, PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/440685
[patent_app_country] => US
[patent_app_date] => 2007-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0005/20100005438.pdf
[firstpage_image] =>[orig_patent_app_number] => 12440685
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/440685 | Processing method of electric information in CAD system, processing device of electric information in CAD system, program and computer-readable storage medium | Oct 9, 2007 | Issued |
Array
(
[id] => 7518005
[patent_doc_number] => 08042087
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-18
[patent_title] => 'Method to design network-on-chip (NOC)-based communication systems'
[patent_app_type] => utility
[patent_app_number] => 12/375525
[patent_app_country] => US
[patent_app_date] => 2007-10-10
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[pdf_file] => patents/08/042/08042087.pdf
[firstpage_image] =>[orig_patent_app_number] => 12375525
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/375525 | Method to design network-on-chip (NOC)-based communication systems | Oct 9, 2007 | Issued |
Array
(
[id] => 4591311
[patent_doc_number] => 07827519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs'
[patent_app_type] => utility
[patent_app_number] => 11/866385
[patent_app_country] => US
[patent_app_date] => 2007-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 9301
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[pdf_file] => patents/07/827/07827519.pdf
[firstpage_image] =>[orig_patent_app_number] => 11866385
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/866385 | Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs | Oct 1, 2007 | Issued |
Array
(
[id] => 5510481
[patent_doc_number] => 20090083688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 11/860775
[patent_app_country] => US
[patent_app_date] => 2007-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0083/20090083688.pdf
[firstpage_image] =>[orig_patent_app_number] => 11860775
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/860775 | Method and apparatus for generating a layout for a transistor | Sep 24, 2007 | Issued |
Array
(
[id] => 5510486
[patent_doc_number] => 20090083693
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'FLASH-BASED UPDATING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS'
[patent_app_type] => utility
[patent_app_number] => 11/861195
[patent_app_country] => US
[patent_app_date] => 2007-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => publications/A1/0083/20090083693.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861195
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861195 | Flash-based updating techniques for high-accuracy high efficiency mask synthesis | Sep 24, 2007 | Issued |
Array
(
[id] => 5510483
[patent_doc_number] => 20090083690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/859965
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[pdf_file] => publications/A1/0083/20090083690.pdf
[firstpage_image] =>[orig_patent_app_number] => 11859965
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859965 | SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT | Sep 23, 2007 | Abandoned |
Array
(
[id] => 4487544
[patent_doc_number] => 07870524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-01-11
[patent_title] => 'Method and system for automating unit performance testing in integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/860475
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/860475 | Method and system for automating unit performance testing in integrated circuit design | Sep 23, 2007 | Issued |
Array
(
[id] => 4582506
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[patent_country] => US
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[patent_issue_date] => 2010-11-23
[patent_title] => 'Method and apparatus for physical implementation of a power optimized circuit design'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/903465 | Method and apparatus for physical implementation of a power optimized circuit design | Sep 20, 2007 | Issued |
Array
(
[id] => 17615
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[patent_title] => 'Methods and systems for physical hierarchy configuration engine and graphical editor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/857985 | Methods and systems for physical hierarchy configuration engine and graphical editor | Sep 18, 2007 | Issued |
Array
(
[id] => 8899592
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[patent_title] => 'Parametric yield improvement flow incorporating sigma to target distance'
[patent_app_type] => utility
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Array
(
[id] => 28588
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[patent_title] => 'Semiconductor integrated circuit for controlling substrate bias'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/892585 | Semiconductor integrated circuit for controlling substrate bias | Aug 23, 2007 | Issued |
Array
(
[id] => 5448188
[patent_doc_number] => 20090049414
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[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE'
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[patent_app_number] => 11/840075
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840075 | METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE | Aug 15, 2007 | Abandoned |
Array
(
[id] => 69215
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[patent_title] => 'Partitioning electronic circuit designs into simulation-ready blocks'
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Array
(
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Array
(
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[patent_title] => 'Multilayer finite difference methods for electrical modeling of packages and printed circuit boards'
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Array
(
[id] => 4735678
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[patent_title] => 'METHOD OF CORRECTING A DESIGNED PATTERN OF A MASK'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/830265 | METHOD OF CORRECTING A DESIGNED PATTERN OF A MASK | Jul 29, 2007 | Abandoned |