Yelena Rossoshek

Array ( [id] => 28592 [patent_doc_number] => 07797661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method and apparatus for describing and managing properties of a transformer coil' [patent_app_type] => utility [patent_app_number] => 11/635929 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7141 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797661.pdf [firstpage_image] =>[orig_patent_app_number] => 11635929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 37839 [patent_doc_number] => 07793243 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-07 [patent_title] => 'Multi-engine static analysis' [patent_app_type] => utility [patent_app_number] => 11/566543 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793243.pdf [firstpage_image] =>[orig_patent_app_number] => 11566543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7798542 [patent_doc_number] => 08127260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-28 [patent_title] => 'Physical layout estimator' [patent_app_type] => utility [patent_app_number] => 11/566196 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7520 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127260.pdf [firstpage_image] =>[orig_patent_app_number] => 11566196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837142 [patent_doc_number] => 20080134117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'SYSTEM AND METHOD FOR EFFICIENT ANALYSIS OF POINT-TO-POINT DELAY CONSTRAINTS IN STATIC TIMING' [patent_app_type] => utility [patent_app_number] => 11/565803 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4771 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134117.pdf [firstpage_image] =>[orig_patent_app_number] => 11565803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837143 [patent_doc_number] => 20080134118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'FLAT PLACEMENT OF CELLS ON NON-INTEGER MULTIPLE HEIGHT ROWS IN A DIGITAL INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 11/565476 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3234 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134118.pdf [firstpage_image] =>[orig_patent_app_number] => 11565476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 245215 [patent_doc_number] => 07590959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Layout system, layout program, and layout method for text or other layout elements along a grid' [patent_app_type] => utility [patent_app_number] => 11/554118 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 24034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590959.pdf [firstpage_image] =>[orig_patent_app_number] => 11554118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830514 [patent_doc_number] => 20080127006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Real-Time Data Stream Decompressor' [patent_app_type] => utility [patent_app_number] => 11/553605 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3001 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127006.pdf [firstpage_image] =>[orig_patent_app_number] => 11553605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 254557 [patent_doc_number] => 07581200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'System and method for analyzing length differences in differential signal paths' [patent_app_type] => utility [patent_app_number] => 11/552975 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1998 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/581/07581200.pdf [firstpage_image] =>[orig_patent_app_number] => 11552975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8810434 [patent_doc_number] => 08448101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Layout method for vertical power transistors having a variable channel width' [patent_app_type] => utility [patent_app_number] => 12/091575 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3241 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12091575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5042341 [patent_doc_number] => 20070094623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Timing, noise, and power analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/588095 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10718 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094623.pdf [firstpage_image] =>[orig_patent_app_number] => 11588095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966952 [patent_doc_number] => 20080109772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'METHOD AND SYSTEM OF INTRODUCING HIERARCHY INTO DESIGN RULE CHECKING TEST CASES AND ROTATION OF TEST CASE DATA' [patent_app_type] => utility [patent_app_number] => 11/552245 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109772.pdf [firstpage_image] =>[orig_patent_app_number] => 11552245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966960 [patent_doc_number] => 20080109780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'METHOD OF AND APPARATUS FOR OPTIMAL PLACEMENT AND VALIDATION OF I/O BLOCKS WITHIN AN ASIC' [patent_app_type] => utility [patent_app_number] => 11/551304 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109780.pdf [firstpage_image] =>[orig_patent_app_number] => 11551304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500708 [patent_doc_number] => 07904843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Systematic generation of scenarios from specification sheet' [patent_app_type] => utility [patent_app_number] => 11/543025 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904843.pdf [firstpage_image] =>[orig_patent_app_number] => 11543025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173701 [patent_doc_number] => 20070074141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Simulation apparatus and simulation method' [patent_app_type] => utility [patent_app_number] => 11/527418 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074141.pdf [firstpage_image] =>[orig_patent_app_number] => 11527418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4940573 [patent_doc_number] => 20080077893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method for verifying interconnected blocks of IP' [patent_app_type] => utility [patent_app_number] => 11/527342 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077893.pdf [firstpage_image] =>[orig_patent_app_number] => 11527342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 188601 [patent_doc_number] => 07650588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Methods and systems for pattern generation based on multiple forms of design data' [patent_app_type] => utility [patent_app_number] => 11/526864 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5466 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650588.pdf [firstpage_image] =>[orig_patent_app_number] => 11526864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 27600 [patent_doc_number] => 07802222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Generalized constraint collection management method' [patent_app_type] => utility [patent_app_number] => 11/527199 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11865 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802222.pdf [firstpage_image] =>[orig_patent_app_number] => 11527199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 235224 [patent_doc_number] => 07600211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Toggle equivalence preserving logic synthesis' [patent_app_type] => utility [patent_app_number] => 11/527198 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 10675 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600211.pdf [firstpage_image] =>[orig_patent_app_number] => 11527198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 171989 [patent_doc_number] => 07669157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches' [patent_app_type] => utility [patent_app_number] => 11/515561 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6331 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669157.pdf [firstpage_image] =>[orig_patent_app_number] => 11515561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4979242 [patent_doc_number] => 20070220477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Circuit-pattern-data correction method and semiconductor-device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/515203 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5129 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220477.pdf [firstpage_image] =>[orig_patent_app_number] => 11515203 [rel_patent_id] =>[rel_patent_doc_number] =>)