Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5115041 [patent_doc_number] => 20070198957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Circuit simulator and circuit simulation program storage medium' [patent_app_type] => utility [patent_app_number] => 11/514947 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4986 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198957.pdf [firstpage_image] =>[orig_patent_app_number] => 11514947 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514947
Transmission circuit simulator and transmission circuit simulation program storage medium Sep 4, 2006 Issued
Array ( [id] => 305962 [patent_doc_number] => 07536669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Generic DMA IP core interface for FPGA platform design' [patent_app_type] => utility [patent_app_number] => 11/513565 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3614 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536669.pdf [firstpage_image] =>[orig_patent_app_number] => 11513565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513565
Generic DMA IP core interface for FPGA platform design Aug 29, 2006 Issued
Array ( [id] => 4499548 [patent_doc_number] => 07886239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Phase coherent differtial structures' [patent_app_type] => utility [patent_app_number] => 11/997352 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2563 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886239.pdf [firstpage_image] =>[orig_patent_app_number] => 11997352 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/997352
Phase coherent differtial structures Jul 25, 2006 Issued
Array ( [id] => 294259 [patent_doc_number] => 07546559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method of optimization of clock gating in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 11/419624 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2683 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546559.pdf [firstpage_image] =>[orig_patent_app_number] => 11419624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/419624
Method of optimization of clock gating in integrated circuit designs May 21, 2006 Issued
Array ( [id] => 127050 [patent_doc_number] => 07712064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Manufacturing aware design of integrated circuit layouts' [patent_app_type] => utility [patent_app_number] => 11/419495 [patent_app_country] => US [patent_app_date] => 2006-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8285 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/712/07712064.pdf [firstpage_image] =>[orig_patent_app_number] => 11419495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/419495
Manufacturing aware design of integrated circuit layouts May 19, 2006 Issued
Array ( [id] => 4591307 [patent_doc_number] => 07827517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-02 [patent_title] => 'Automated register definition, builder and integration framework' [patent_app_type] => utility [patent_app_number] => 11/419305 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5116 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827517.pdf [firstpage_image] =>[orig_patent_app_number] => 11419305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/419305
Automated register definition, builder and integration framework May 18, 2006 Issued
Array ( [id] => 5030093 [patent_doc_number] => 20070271540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS' [patent_app_type] => utility [patent_app_number] => 11/383565 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2179 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271540.pdf [firstpage_image] =>[orig_patent_app_number] => 11383565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/383565
STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS May 15, 2006 Abandoned
Array ( [id] => 5644037 [patent_doc_number] => 20060282492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Determining mutual inductance between intentional inductors' [patent_app_type] => utility [patent_app_number] => 11/435426 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23551 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282492.pdf [firstpage_image] =>[orig_patent_app_number] => 11435426 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435426
Determining mutual inductance between intentional inductors May 15, 2006 Issued
Array ( [id] => 336996 [patent_doc_number] => 07509623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/381262 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 49 [patent_no_of_words] => 8397 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509623.pdf [firstpage_image] =>[orig_patent_app_number] => 11381262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381262
Manufacturing method of semiconductor device May 1, 2006 Issued
Array ( [id] => 5836043 [patent_doc_number] => 20060247875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Apparatus and method of delay calculation for structured ASIC' [patent_app_type] => utility [patent_app_number] => 11/414295 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7368 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20060247875.pdf [firstpage_image] =>[orig_patent_app_number] => 11414295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414295
Apparatus and method of delay calculation for structured ASIC Apr 30, 2006 Issued
Array ( [id] => 4560326 [patent_doc_number] => 07877710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method and apparatus for deriving signal activities for power analysis and optimization' [patent_app_type] => utility [patent_app_number] => 11/414855 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8865 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877710.pdf [firstpage_image] =>[orig_patent_app_number] => 11414855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414855
Method and apparatus for deriving signal activities for power analysis and optimization Apr 30, 2006 Issued
Array ( [id] => 4990793 [patent_doc_number] => 20070157134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Method for testing a hardware circuit block written in a hardware description language' [patent_app_type] => utility [patent_app_number] => 11/407955 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2286 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157134.pdf [firstpage_image] =>[orig_patent_app_number] => 11407955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407955
Method for testing a hardware circuit block written in a hardware description language Apr 20, 2006 Abandoned
Array ( [id] => 7692322 [patent_doc_number] => 20070231711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'System and method for making photomasks' [patent_app_type] => utility [patent_app_number] => 11/392869 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7063 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20070231711.pdf [firstpage_image] =>[orig_patent_app_number] => 11392869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/392869
Automated circuit design dimension change responsive to low contrast condition determination in photomask phase pattern Mar 29, 2006 Issued
Array ( [id] => 7692323 [patent_doc_number] => 20070231710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method and system for forming a photomask pattern' [patent_app_type] => utility [patent_app_number] => 11/392655 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6903 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20070231710.pdf [firstpage_image] =>[orig_patent_app_number] => 11392655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/392655
Method and system for forming a photomask pattern Mar 29, 2006 Abandoned
Array ( [id] => 4979239 [patent_doc_number] => 20070220474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for facilitating power/ground wiring in a layout' [patent_app_type] => utility [patent_app_number] => 11/374965 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2046 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220474.pdf [firstpage_image] =>[orig_patent_app_number] => 11374965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/374965
Method for facilitating power/ground wiring in a layout Mar 14, 2006 Abandoned
Array ( [id] => 8716256 [patent_doc_number] => 08402409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/373744 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3871 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11373744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/373744
Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit Mar 9, 2006 Issued
Array ( [id] => 5836654 [patent_doc_number] => 20060248486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Manufacturing a clock distribution network in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/372235 [patent_app_country] => US [patent_app_date] => 2006-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2812 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248486.pdf [firstpage_image] =>[orig_patent_app_number] => 11372235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372235
Manufacturing a clock distribution network in an integrated circuit Mar 8, 2006 Issued
Array ( [id] => 4449099 [patent_doc_number] => 07865851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Capacitance extraction of intergrated circuits with floating fill' [patent_app_type] => utility [patent_app_number] => 11/369565 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9141 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865851.pdf [firstpage_image] =>[orig_patent_app_number] => 11369565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369565
Capacitance extraction of intergrated circuits with floating fill Mar 5, 2006 Issued
Array ( [id] => 5071650 [patent_doc_number] => 20070192752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Influence-based circuit design' [patent_app_type] => utility [patent_app_number] => 11/354425 [patent_app_country] => US [patent_app_date] => 2006-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192752.pdf [firstpage_image] =>[orig_patent_app_number] => 11354425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354425
Influence-based circuit design Feb 14, 2006 Issued
Array ( [id] => 372210 [patent_doc_number] => 07478346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Debugging system for gate level IC designs' [patent_app_type] => utility [patent_app_number] => 11/342125 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3647 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478346.pdf [firstpage_image] =>[orig_patent_app_number] => 11342125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342125
Debugging system for gate level IC designs Jan 25, 2006 Issued
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