
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5143901
[patent_doc_number] => 20070006117
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[patent_title] => 'Method for optimally converting a circuit design into a semiconductor device'
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Array
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[patent_issue_date] => 2008-11-11
[patent_title] => 'Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies'
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Array
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Array
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[patent_title] => 'Method for designing semiconductor device and method for evaluating reliability thereof'
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Array
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[patent_title] => 'Efficient method for mapping a logic design on field programmable gate arrays'
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Array
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Array
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[patent_title] => 'A METHOD , APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/275275 | Semiconductor yield estimation | Dec 20, 2005 | Issued |
Array
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Array
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[patent_title] => 'Topology-driven apparatus, method and computer program product for developing a wiring design'
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Array
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Array
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Array
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Array
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