Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5143901 [patent_doc_number] => 20070006117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method for optimally converting a circuit design into a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/333925 [patent_app_country] => US [patent_app_date] => 2006-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006117.pdf [firstpage_image] =>[orig_patent_app_number] => 11333925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333925
Method for optimally converting a circuit design into a semiconductor device Jan 17, 2006 Issued
Array ( [id] => 598857 [patent_doc_number] => 07451421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies' [patent_app_type] => utility [patent_app_number] => 11/333865 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 14165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451421.pdf [firstpage_image] =>[orig_patent_app_number] => 11333865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333865
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies Jan 16, 2006 Issued
Array ( [id] => 201057 [patent_doc_number] => 07640522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method and system for placing layout objects in a standard-cell layout' [patent_app_type] => utility [patent_app_number] => 11/331605 [patent_app_country] => US [patent_app_date] => 2006-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9787 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640522.pdf [firstpage_image] =>[orig_patent_app_number] => 11331605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331605
Method and system for placing layout objects in a standard-cell layout Jan 13, 2006 Issued
Array ( [id] => 5696116 [patent_doc_number] => 20060156263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method for designing semiconductor device and method for evaluating reliability thereof' [patent_app_type] => utility [patent_app_number] => 11/326355 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11620 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156263.pdf [firstpage_image] =>[orig_patent_app_number] => 11326355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/326355
Methods for designing, evaluating and manufacturing semiconductor devices Jan 5, 2006 Issued
Array ( [id] => 4989934 [patent_doc_number] => 20070156275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Automated metrology recipe generation' [patent_app_type] => utility [patent_app_number] => 11/323255 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5494 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20070156275.pdf [firstpage_image] =>[orig_patent_app_number] => 11323255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323255
Automated metrology recipe generation Dec 29, 2005 Issued
Array ( [id] => 5621371 [patent_doc_number] => 20060190906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Efficient method for mapping a logic design on field programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 11/319015 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4537 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190906.pdf [firstpage_image] =>[orig_patent_app_number] => 11319015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319015
Efficient method for mapping a logic design on field programmable gate arrays Dec 26, 2005 Issued
Array ( [id] => 329730 [patent_doc_number] => 07516425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method for generating minimal leakage current input vector using heuristics' [patent_app_type] => utility [patent_app_number] => 11/315695 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2103 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516425.pdf [firstpage_image] =>[orig_patent_app_number] => 11315695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315695
Method for generating minimal leakage current input vector using heuristics Dec 21, 2005 Issued
Array ( [id] => 5122005 [patent_doc_number] => 20070143720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'A METHOD , APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION' [patent_app_type] => utility [patent_app_number] => 11/275275 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143720.pdf [firstpage_image] =>[orig_patent_app_number] => 11275275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/275275
Semiconductor yield estimation Dec 20, 2005 Issued
Array ( [id] => 136713 [patent_doc_number] => 07703064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Multilayered circuit board design support method, program, and apparatus for suppressing thermal diffusion from solid-layer conductor to through hole' [patent_app_type] => utility [patent_app_number] => 11/311655 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703064.pdf [firstpage_image] =>[orig_patent_app_number] => 11311655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311655
Multilayered circuit board design support method, program, and apparatus for suppressing thermal diffusion from solid-layer conductor to through hole Dec 19, 2005 Issued
Array ( [id] => 5120184 [patent_doc_number] => 20070141899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Topology-driven apparatus, method and computer program product for developing a wiring design' [patent_app_type] => utility [patent_app_number] => 11/305965 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5446 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141899.pdf [firstpage_image] =>[orig_patent_app_number] => 11305965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305965
Topology-driven apparatus, method and computer program product for developing a wiring design Dec 18, 2005 Issued
Array ( [id] => 5122010 [patent_doc_number] => 20070143725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage' [patent_app_type] => utility [patent_app_number] => 11/311515 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143725.pdf [firstpage_image] =>[orig_patent_app_number] => 11311515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311515
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Dec 18, 2005 Issued
Array ( [id] => 5647438 [patent_doc_number] => 20060133170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Memory circuit' [patent_app_type] => utility [patent_app_number] => 11/304775 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5127 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133170.pdf [firstpage_image] =>[orig_patent_app_number] => 11304775 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304775
Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit Dec 15, 2005 Issued
Array ( [id] => 591104 [patent_doc_number] => 07464356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method and apparatus for diffusion based cell placement migration' [patent_app_type] => utility [patent_app_number] => 11/304955 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5052 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464356.pdf [firstpage_image] =>[orig_patent_app_number] => 11304955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304955
Method and apparatus for diffusion based cell placement migration Dec 14, 2005 Issued
Array ( [id] => 823634 [patent_doc_number] => 07409667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-05 [patent_title] => 'Techniques for modeling a circuit board structure' [patent_app_type] => utility [patent_app_number] => 11/303602 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409667.pdf [firstpage_image] =>[orig_patent_app_number] => 11303602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303602
Techniques for modeling a circuit board structure Dec 14, 2005 Issued
Array ( [id] => 336975 [patent_doc_number] => 07509605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Extending incremental verification of circuit design to encompass verification restraints' [patent_app_type] => utility [patent_app_number] => 11/301112 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509605.pdf [firstpage_image] =>[orig_patent_app_number] => 11301112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301112
Extending incremental verification of circuit design to encompass verification restraints Dec 11, 2005 Issued
Array ( [id] => 5713715 [patent_doc_number] => 20060077078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Command user interface with programmable decoder' [patent_app_type] => utility [patent_app_number] => 11/288471 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20060077078.pdf [firstpage_image] =>[orig_patent_app_number] => 11288471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288471
Command user interface with programmable decoder Nov 28, 2005 Abandoned
Array ( [id] => 4528418 [patent_doc_number] => 07934184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Integrated circuit design using modified cells' [patent_app_type] => utility [patent_app_number] => 11/273685 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 7687 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934184.pdf [firstpage_image] =>[orig_patent_app_number] => 11273685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273685
Integrated circuit design using modified cells Nov 13, 2005 Issued
Array ( [id] => 4592935 [patent_doc_number] => 07853911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method and apparatus for performing path-level skew optimization and analysis for a logic design' [patent_app_type] => utility [patent_app_number] => 11/267655 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8607 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853911.pdf [firstpage_image] =>[orig_patent_app_number] => 11267655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267655
Method and apparatus for performing path-level skew optimization and analysis for a logic design Nov 3, 2005 Issued
Array ( [id] => 49075 [patent_doc_number] => 07779380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Data processing apparatus including reconfigurable logic circuit' [patent_app_type] => utility [patent_app_number] => 11/718195 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 10668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779380.pdf [firstpage_image] =>[orig_patent_app_number] => 11718195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718195
Data processing apparatus including reconfigurable logic circuit Oct 27, 2005 Issued
Array ( [id] => 4574036 [patent_doc_number] => 07962868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method for forming a semiconductor device using optical proximity correction for the optical lithography' [patent_app_type] => utility [patent_app_number] => 12/091695 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962868.pdf [firstpage_image] =>[orig_patent_app_number] => 12091695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/091695
Method for forming a semiconductor device using optical proximity correction for the optical lithography Oct 27, 2005 Issued
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