Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5746666 [patent_doc_number] => 20060109596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Electrostatic discharge testing method and semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 11/243355 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109596.pdf [firstpage_image] =>[orig_patent_app_number] => 11243355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243355
Electrostatic discharge testing method and semiconductor device fabrication method Oct 2, 2005 Issued
Array ( [id] => 5030420 [patent_doc_number] => 20070094959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Phase-shifting masks with sub-wavelength diffractive optical elements' [patent_app_type] => utility [patent_app_number] => 11/242165 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094959.pdf [firstpage_image] =>[orig_patent_app_number] => 11242165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242165
Phase-shifting masks with sub-wavelength diffractive optical elements Sep 29, 2005 Issued
Array ( [id] => 108165 [patent_doc_number] => 07725865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers' [patent_app_type] => utility [patent_app_number] => 11/236532 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5823 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725865.pdf [firstpage_image] =>[orig_patent_app_number] => 11236532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236532
Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers Sep 27, 2005 Issued
Array ( [id] => 362963 [patent_doc_number] => 07487481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Receiver circuit for on chip timing adjustment' [patent_app_type] => utility [patent_app_number] => 11/232675 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5495 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487481.pdf [firstpage_image] =>[orig_patent_app_number] => 11232675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232675
Receiver circuit for on chip timing adjustment Sep 21, 2005 Issued
Array ( [id] => 4743738 [patent_doc_number] => 20080088339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Hard Macro with Configurable Side Input/Output Terminals, for a Subsystem' [patent_app_type] => utility [patent_app_number] => 11/576685 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3640 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20080088339.pdf [firstpage_image] =>[orig_patent_app_number] => 11576685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/576685
Hard macro with configurable side input/output terminals, for a subsystem Sep 20, 2005 Issued
Array ( [id] => 7589599 [patent_doc_number] => 07665054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Optimizing circuit layouts by configuring rooms for placing devices' [patent_app_type] => utility [patent_app_number] => 11/231055 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7927 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665054.pdf [firstpage_image] =>[orig_patent_app_number] => 11231055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231055
Optimizing circuit layouts by configuring rooms for placing devices Sep 18, 2005 Issued
Array ( [id] => 298004 [patent_doc_number] => 07543249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Embedded switchable power ring' [patent_app_type] => utility [patent_app_number] => 11/230085 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4007 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543249.pdf [firstpage_image] =>[orig_patent_app_number] => 11230085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230085
Embedded switchable power ring Sep 18, 2005 Issued
Array ( [id] => 201063 [patent_doc_number] => 07640526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Modular partial reconfiguration' [patent_app_type] => utility [patent_app_number] => 11/225225 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8701 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640526.pdf [firstpage_image] =>[orig_patent_app_number] => 11225225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225225
Modular partial reconfiguration Sep 11, 2005 Issued
Array ( [id] => 5898329 [patent_doc_number] => 20060043562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Circuit device and manufacture method for circuit device' [patent_app_type] => utility [patent_app_number] => 11/212655 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7420 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043562.pdf [firstpage_image] =>[orig_patent_app_number] => 11212655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212655
Circuit device and manufacture method for circuit device Aug 28, 2005 Abandoned
Array ( [id] => 5627177 [patent_doc_number] => 20060265682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Manufacturing aware design and design aware manufacturing' [patent_app_type] => utility [patent_app_number] => 11/214472 [patent_app_country] => US [patent_app_date] => 2005-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11158 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265682.pdf [firstpage_image] =>[orig_patent_app_number] => 11214472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214472
Manufacturing aware design and design aware manufacturing Aug 27, 2005 Issued
Array ( [id] => 333386 [patent_doc_number] => 07512918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Multimode delay analysis for simplifying integrated circuit design timing models' [patent_app_type] => utility [patent_app_number] => 11/205365 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3341 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512918.pdf [firstpage_image] =>[orig_patent_app_number] => 11205365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205365
Multimode delay analysis for simplifying integrated circuit design timing models Aug 16, 2005 Issued
Array ( [id] => 5796850 [patent_doc_number] => 20060033527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'PLD architecture for flexible placement of IP functions blocks' [patent_app_type] => utility [patent_app_number] => 11/202616 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3585 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033527.pdf [firstpage_image] =>[orig_patent_app_number] => 11202616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202616
PLD architecture for flexible placement of IP function blocks Aug 11, 2005 Issued
Array ( [id] => 801767 [patent_doc_number] => 07426709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-16 [patent_title] => 'Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system' [patent_app_type] => utility [patent_app_number] => 11/198785 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3349 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/426/07426709.pdf [firstpage_image] =>[orig_patent_app_number] => 11198785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198785
Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system Aug 4, 2005 Issued
Array ( [id] => 136716 [patent_doc_number] => 07703066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product' [patent_app_type] => utility [patent_app_number] => 11/185945 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5583 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703066.pdf [firstpage_image] =>[orig_patent_app_number] => 11185945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185945
Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product Jul 20, 2005 Issued
Array ( [id] => 7599890 [patent_doc_number] => 07386823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Rule-based schematic diagram generator' [patent_app_type] => utility [patent_app_number] => 11/186165 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 7188 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386823.pdf [firstpage_image] =>[orig_patent_app_number] => 11186165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/186165
Rule-based schematic diagram generator Jul 19, 2005 Issued
Array ( [id] => 158070 [patent_doc_number] => 07685554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Determination of data rate and data type in a high-level electronic design' [patent_app_type] => utility [patent_app_number] => 11/185125 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6518 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685554.pdf [firstpage_image] =>[orig_patent_app_number] => 11185125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185125
Determination of data rate and data type in a high-level electronic design Jul 19, 2005 Issued
Array ( [id] => 5073720 [patent_doc_number] => 20070013695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Digitally obtaining contours of fabricated polygons' [patent_app_type] => utility [patent_app_number] => 11/182615 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20070013695.pdf [firstpage_image] =>[orig_patent_app_number] => 11182615 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182615
Digitally obtaining contours of fabricated polygons Jul 14, 2005 Issued
Array ( [id] => 4996290 [patent_doc_number] => 20070011635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Method of selling integrated circuit dies for multi-chip packages' [patent_app_type] => utility [patent_app_number] => 11/174495 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2708 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011635.pdf [firstpage_image] =>[orig_patent_app_number] => 11174495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174495
Method of selling integrated circuit dies for multi-chip packages Jul 5, 2005 Issued
Array ( [id] => 47986 [patent_doc_number] => 07784015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method for generating a mask layout and constructing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/175775 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1719 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784015.pdf [firstpage_image] =>[orig_patent_app_number] => 11175775 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175775
Method for generating a mask layout and constructing an integrated circuit Jul 4, 2005 Issued
Array ( [id] => 336990 [patent_doc_number] => 07509619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages' [patent_app_type] => utility [patent_app_number] => 11/159085 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8147 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509619.pdf [firstpage_image] =>[orig_patent_app_number] => 11159085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159085
Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages Jun 21, 2005 Issued
Menu