Yelena Rossoshek

Array ( [id] => 6979772 [patent_doc_number] => 20050289490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits' [patent_app_type] => utility [patent_app_number] => 11/159283 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4121 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289490.pdf [firstpage_image] =>[orig_patent_app_number] => 11159283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5604139 [patent_doc_number] => 20060294486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Manhattan routing with minimized distance to destination points' [patent_app_type] => utility [patent_app_number] => 11/151045 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294486.pdf [firstpage_image] =>[orig_patent_app_number] => 11151045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 336966 [patent_doc_number] => 07509599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method and apparatus for performing formal verification using data-flow graphs' [patent_app_type] => utility [patent_app_number] => 11/150685 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 108 [patent_no_of_words] => 41413 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509599.pdf [firstpage_image] =>[orig_patent_app_number] => 11150685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 302238 [patent_doc_number] => 07539957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks' [patent_app_type] => utility [patent_app_number] => 11/139165 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6413 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539957.pdf [firstpage_image] =>[orig_patent_app_number] => 11139165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 388873 [patent_doc_number] => 07305649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Automatic generation of a streaming processor circuit' [patent_app_type] => utility [patent_app_number] => 11/109915 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6108 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305649.pdf [firstpage_image] =>[orig_patent_app_number] => 11109915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 860581 [patent_doc_number] => 07376916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Performing a constrained optimization to determine circuit parameters' [patent_app_type] => utility [patent_app_number] => 11/111655 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7425 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376916.pdf [firstpage_image] =>[orig_patent_app_number] => 11111655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 321677 [patent_doc_number] => 07523438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Method for improved lithographic patterning utilizing optimized illumination conditions and high transmission attenuated PSM' [patent_app_type] => utility [patent_app_number] => 11/108665 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 8882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523438.pdf [firstpage_image] =>[orig_patent_app_number] => 11108665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 355772 [patent_doc_number] => 07493578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Correlation of data from design analysis tools with design blocks in a high-level modeling system' [patent_app_type] => utility [patent_app_number] => 11/083667 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4402 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493578.pdf [firstpage_image] =>[orig_patent_app_number] => 11083667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7207715 [patent_doc_number] => 20050166173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Design data format and hierarchy management for processing' [patent_app_type] => utility [patent_app_number] => 11/083697 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5603 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166173.pdf [firstpage_image] =>[orig_patent_app_number] => 11083697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 97605 [patent_doc_number] => 07739638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence' [patent_app_type] => utility [patent_app_number] => 11/072605 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8494 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739638.pdf [firstpage_image] =>[orig_patent_app_number] => 11072605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 223671 [patent_doc_number] => 07610569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Chip design verification apparatus and data communication method for the same' [patent_app_type] => utility [patent_app_number] => 10/589595 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9909 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610569.pdf [firstpage_image] =>[orig_patent_app_number] => 10589595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7176190 [patent_doc_number] => 20050203722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Power distribution network simulation method using variable reduction method' [patent_app_type] => utility [patent_app_number] => 11/056955 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20050203722.pdf [firstpage_image] =>[orig_patent_app_number] => 11056955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7140946 [patent_doc_number] => 20050183048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Method to simulate the influence of production-caused variations on electrical interconnect properties of semiconductor layouts' [patent_app_type] => utility [patent_app_number] => 11/044625 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3642 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20050183048.pdf [firstpage_image] =>[orig_patent_app_number] => 11044625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7006940 [patent_doc_number] => 20050172253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Automatic placement and routing device, method for placement and routing of semiconductor device, semiconductor device and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 11/041995 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6866 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172253.pdf [firstpage_image] =>[orig_patent_app_number] => 11041995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5696121 [patent_doc_number] => 20060156268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Circuit design platform' [patent_app_type] => utility [patent_app_number] => 11/036485 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3685 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156268.pdf [firstpage_image] =>[orig_patent_app_number] => 11036485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 385013 [patent_doc_number] => 07308673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Method and apparatus for correcting 3D mask effects' [patent_app_type] => utility [patent_app_number] => 11/033415 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2872 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/308/07308673.pdf [firstpage_image] =>[orig_patent_app_number] => 11033415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 856487 [patent_doc_number] => 07380226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Systems, methods, and apparatus to perform logic synthesis preserving high-level specification' [patent_app_type] => utility [patent_app_number] => 11/027085 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8305 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380226.pdf [firstpage_image] =>[orig_patent_app_number] => 11027085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5657846 [patent_doc_number] => 20060143582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Generating testcases based on numbers of testcases previously generated' [patent_app_type] => utility [patent_app_number] => 11/021525 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143582.pdf [firstpage_image] =>[orig_patent_app_number] => 11021525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7107663 [patent_doc_number] => 20050108669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Layout method, layout apparatus, layout program and recording medium thereof' [patent_app_type] => utility [patent_app_number] => 11/019365 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108669.pdf [firstpage_image] =>[orig_patent_app_number] => 11019365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 905178 [patent_doc_number] => 07340697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies' [patent_app_type] => utility [patent_app_number] => 11/019885 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3715 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340697.pdf [firstpage_image] =>[orig_patent_app_number] => 11019885 [rel_patent_id] =>[rel_patent_doc_number] =>)