
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7077517
[patent_doc_number] => 20050149895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Delay library generation method and delay library generation device'
[patent_app_type] => utility
[patent_app_number] => 11/016805
[patent_app_country] => US
[patent_app_date] => 2004-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7975
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20050149895.pdf
[firstpage_image] =>[orig_patent_app_number] => 11016805
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/016805 | Delay library generation method and delay library generation device | Dec 20, 2004 | Abandoned |
Array
(
[id] => 836500
[patent_doc_number] => 07398492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Rules and directives for validating correct data used in the design of semiconductor products'
[patent_app_type] => utility
[patent_app_number] => 11/017015
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11561
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/398/07398492.pdf
[firstpage_image] =>[orig_patent_app_number] => 11017015
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/017015 | Rules and directives for validating correct data used in the design of semiconductor products | Dec 19, 2004 | Issued |
Array
(
[id] => 5917051
[patent_doc_number] => 20060129962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Cell builder for different layer stacks'
[patent_app_type] => utility
[patent_app_number] => 11/010745
[patent_app_country] => US
[patent_app_date] => 2004-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2704
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20060129962.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010745
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010745 | Cell builder for different layer stacks | Dec 12, 2004 | Issued |
Array
(
[id] => 929680
[patent_doc_number] => 07315993
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-01
[patent_title] => 'Verification of RRAM tiling netlist'
[patent_app_type] => utility
[patent_app_number] => 10/999468
[patent_app_country] => US
[patent_app_date] => 2004-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5300
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/315/07315993.pdf
[firstpage_image] =>[orig_patent_app_number] => 10999468
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/999468 | Verification of RRAM tiling netlist | Nov 29, 2004 | Issued |
Array
(
[id] => 7149342
[patent_doc_number] => 20050120326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Method for producing for a mask a mask layout which avoids aberrations'
[patent_app_type] => utility
[patent_app_number] => 10/997695
[patent_app_country] => US
[patent_app_date] => 2004-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5503
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20050120326.pdf
[firstpage_image] =>[orig_patent_app_number] => 10997695
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/997695 | Method for producing for a mask a mask layout which avoids aberrations | Nov 23, 2004 | Abandoned |
Array
(
[id] => 400779
[patent_doc_number] => 07296252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Clustering techniques for faster and better placement of VLSI circuits'
[patent_app_type] => utility
[patent_app_number] => 10/996293
[patent_app_country] => US
[patent_app_date] => 2004-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5745
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/296/07296252.pdf
[firstpage_image] =>[orig_patent_app_number] => 10996293
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996293 | Clustering techniques for faster and better placement of VLSI circuits | Nov 21, 2004 | Issued |
Array
(
[id] => 836507
[patent_doc_number] => 07398497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method'
[patent_app_type] => utility
[patent_app_number] => 10/992755
[patent_app_country] => US
[patent_app_date] => 2004-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 62
[patent_no_of_words] => 18077
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/398/07398497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10992755
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/992755 | Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method | Nov 21, 2004 | Issued |
Array
(
[id] => 7077503
[patent_doc_number] => 20050149887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Design method and system for optimum performance in integrated circuits that use power management'
[patent_app_type] => utility
[patent_app_number] => 10/993815
[patent_app_country] => US
[patent_app_date] => 2004-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3200
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20050149887.pdf
[firstpage_image] =>[orig_patent_app_number] => 10993815
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/993815 | Design method and system for optimum performance in integrated circuits that use power management | Nov 18, 2004 | Issued |
Array
(
[id] => 823638
[patent_doc_number] => 07409670
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-08-05
[patent_title] => 'Scheduling logic on a programmable device implemented using a high-level language'
[patent_app_type] => utility
[patent_app_number] => 10/993572
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8776
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/409/07409670.pdf
[firstpage_image] =>[orig_patent_app_number] => 10993572
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/993572 | Scheduling logic on a programmable device implemented using a high-level language | Nov 15, 2004 | Issued |
Array
(
[id] => 5867228
[patent_doc_number] => 20060101360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Systems and methods of simulating signal coupling'
[patent_app_type] => utility
[patent_app_number] => 10/984245
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3226
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20060101360.pdf
[firstpage_image] =>[orig_patent_app_number] => 10984245
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984245 | Systems and methods of simulating signal coupling | Nov 8, 2004 | Issued |
Array
(
[id] => 5867231
[patent_doc_number] => 20060101363
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Method of associating timing violations with critical structures in an integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 10/984115
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3154
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20060101363.pdf
[firstpage_image] =>[orig_patent_app_number] => 10984115
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984115 | Method of associating timing violations with critical structures in an integrated circuit design | Nov 7, 2004 | Issued |
Array
(
[id] => 895090
[patent_doc_number] => 07350183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'Method for improving optical proximity correction'
[patent_app_type] => utility
[patent_app_number] => 10/904355
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 5626
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/350/07350183.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904355
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904355 | Method for improving optical proximity correction | Nov 4, 2004 | Issued |
Array
(
[id] => 473074
[patent_doc_number] => 07234124
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-19
[patent_title] => 'Method and apparatus for performing power routing on a voltage island within an integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 10/980575
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2357
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/234/07234124.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980575
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980575 | Method and apparatus for performing power routing on a voltage island within an integrated circuit chip | Nov 2, 2004 | Issued |
Array
(
[id] => 6954034
[patent_doc_number] => 20050229129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'System and method for verifying signal propagation delays of circuit traces of a PCB layout'
[patent_app_type] => utility
[patent_app_number] => 10/977635
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2385
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20050229129.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977635
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977635 | System and method for verifying signal propagation delays of circuit traces of a PCB layout | Oct 28, 2004 | Issued |
Array
(
[id] => 398028
[patent_doc_number] => 07302651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-27
[patent_title] => 'Technology migration for integrated circuits with radical design restrictions'
[patent_app_type] => utility
[patent_app_number] => 10/904225
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 29
[patent_no_of_words] => 11657
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/302/07302651.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904225 | Technology migration for integrated circuits with radical design restrictions | Oct 28, 2004 | Issued |
Array
(
[id] => 5867226
[patent_doc_number] => 20060101358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Circuit design simulation'
[patent_app_type] => utility
[patent_app_number] => 10/975145
[patent_app_country] => US
[patent_app_date] => 2004-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3938
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20060101358.pdf
[firstpage_image] =>[orig_patent_app_number] => 10975145
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/975145 | Circuit design simulation | Oct 27, 2004 | Abandoned |
Array
(
[id] => 7149316
[patent_doc_number] => 20050120316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Mutual inductance extraction using dipole approximations'
[patent_app_type] => utility
[patent_app_number] => 10/972025
[patent_app_country] => US
[patent_app_date] => 2004-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 16354
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20050120316.pdf
[firstpage_image] =>[orig_patent_app_number] => 10972025
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/972025 | Mutual inductance extraction using dipole approximations | Oct 20, 2004 | Issued |
Array
(
[id] => 599532
[patent_doc_number] => 07444614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal'
[patent_app_type] => utility
[patent_app_number] => 10/968925
[patent_app_country] => US
[patent_app_date] => 2004-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7069
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/444/07444614.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968925 | Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal | Oct 20, 2004 | Issued |
Array
(
[id] => 5809526
[patent_doc_number] => 20060095882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Distributed electronic design automation environment'
[patent_app_type] => utility
[patent_app_number] => 10/935749
[patent_app_country] => US
[patent_app_date] => 2004-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 70
[patent_figures_cnt] => 70
[patent_no_of_words] => 25771
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20060095882.pdf
[firstpage_image] =>[orig_patent_app_number] => 10935749
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/935749 | Distributed electronic design automation environment | Sep 7, 2004 | Issued |
Array
(
[id] => 444654
[patent_doc_number] => 07260797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-21
[patent_title] => 'Method and apparatus for estimating parasitic capacitance'
[patent_app_type] => utility
[patent_app_number] => 10/935765
[patent_app_country] => US
[patent_app_date] => 2004-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4723
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/260/07260797.pdf
[firstpage_image] =>[orig_patent_app_number] => 10935765
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/935765 | Method and apparatus for estimating parasitic capacitance | Sep 6, 2004 | Issued |