Yelena Rossoshek

Array ( [id] => 438586 [patent_doc_number] => 07263672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Methods, systems, and data models for describing an electrical device' [patent_app_type] => utility [patent_app_number] => 10/933535 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4623 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263672.pdf [firstpage_image] =>[orig_patent_app_number] => 10933535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 900368 [patent_doc_number] => 07343571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model' [patent_app_type] => utility [patent_app_number] => 10/933335 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 59 [patent_no_of_words] => 37903 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343571.pdf [firstpage_image] =>[orig_patent_app_number] => 10933335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5712047 [patent_doc_number] => 20060053393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Method of improving routes of nets in circuits' [patent_app_type] => utility [patent_app_number] => 10/934165 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7461 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20060053393.pdf [firstpage_image] =>[orig_patent_app_number] => 10934165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7223521 [patent_doc_number] => 20050055654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method for checking an IC layout' [patent_app_type] => utility [patent_app_number] => 10/924505 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3225 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055654.pdf [firstpage_image] =>[orig_patent_app_number] => 10924505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7223250 [patent_doc_number] => 20050055612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Design supporting apparatus' [patent_app_type] => utility [patent_app_number] => 10/921455 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4708 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055612.pdf [firstpage_image] =>[orig_patent_app_number] => 10921455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7119045 [patent_doc_number] => 20050071792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Secure exchange of information in electronic design automation' [patent_app_type] => utility [patent_app_number] => 10/920988 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071792.pdf [firstpage_image] =>[orig_patent_app_number] => 10920988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 864578 [patent_doc_number] => 07373631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Methods of producing application-specific integrated circuit equivalents of programmable logic' [patent_app_type] => utility [patent_app_number] => 10/916305 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3754 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373631.pdf [firstpage_image] =>[orig_patent_app_number] => 10916305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 411591 [patent_doc_number] => 07287235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Method of simplifying a circuit for equivalence checking' [patent_app_type] => utility [patent_app_number] => 10/912985 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6784 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287235.pdf [firstpage_image] =>[orig_patent_app_number] => 10912985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5822228 [patent_doc_number] => 20060026541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method and apparatus for expediting convergence in model-based OPC' [patent_app_type] => utility [patent_app_number] => 10/910539 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3967 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026541.pdf [firstpage_image] =>[orig_patent_app_number] => 10910539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 846351 [patent_doc_number] => 07389490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities' [patent_app_type] => utility [patent_app_number] => 10/902595 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 58 [patent_no_of_words] => 48477 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389490.pdf [firstpage_image] =>[orig_patent_app_number] => 10902595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5882719 [patent_doc_number] => 20060031802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Clustering-based multilevel quadratic placement' [patent_app_type] => utility [patent_app_number] => 10/896495 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3508 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031802.pdf [firstpage_image] =>[orig_patent_app_number] => 10896495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 583356 [patent_doc_number] => 07159203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Differential delay-line' [patent_app_type] => utility [patent_app_number] => 10/897745 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2913 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159203.pdf [firstpage_image] =>[orig_patent_app_number] => 10897745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 490716 [patent_doc_number] => 07222312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Secure exchange of information in electronic design automation' [patent_app_type] => utility [patent_app_number] => 10/895485 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6485 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222312.pdf [firstpage_image] =>[orig_patent_app_number] => 10895485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5795151 [patent_doc_number] => 20060015832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops' [patent_app_type] => utility [patent_app_number] => 10/889795 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3283 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015832.pdf [firstpage_image] =>[orig_patent_app_number] => 10889795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 905181 [patent_doc_number] => 07340699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Analysis apparatus for semiconductor LSI circuit electrostatic discharge by calculating inter-pad voltage between pads' [patent_app_type] => utility [patent_app_number] => 10/890025 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 4573 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340699.pdf [firstpage_image] =>[orig_patent_app_number] => 10890025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 922287 [patent_doc_number] => 07325217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Automatic wiring method for the crosstalk reduction' [patent_app_type] => utility [patent_app_number] => 10/888635 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 9918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325217.pdf [firstpage_image] =>[orig_patent_app_number] => 10888635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 905179 [patent_doc_number] => 07340698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components' [patent_app_type] => utility [patent_app_number] => 10/881195 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10472 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340698.pdf [firstpage_image] =>[orig_patent_app_number] => 10881195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 375071 [patent_doc_number] => 07475379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Methods and systems for layout and routing using alternating aperture phase shift masks' [patent_app_type] => utility [patent_app_number] => 10/710165 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6837 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475379.pdf [firstpage_image] =>[orig_patent_app_number] => 10710165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 555931 [patent_doc_number] => 07181717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-20 [patent_title] => 'Method and apparatus for placement of components onto programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/868625 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4958 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181717.pdf [firstpage_image] =>[orig_patent_app_number] => 10868625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7450972 [patent_doc_number] => 20040268276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Osculating models for predicting the operation of a circuit structure' [patent_app_type] => new [patent_app_number] => 10/856425 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5286 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268276.pdf [firstpage_image] =>[orig_patent_app_number] => 10856425 [rel_patent_id] =>[rel_patent_doc_number] =>)