Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7057483 [patent_doc_number] => 20050278658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Standard cell library having cell drive strengths selected according to delay' [patent_app_type] => utility [patent_app_number] => 10/856345 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4495 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278658.pdf [firstpage_image] =>[orig_patent_app_number] => 10856345 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856345
Standard cell library having cell drive strengths selected according to delay May 26, 2004 Issued
Array ( [id] => 372223 [patent_doc_number] => 07478355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Input/output circuits with programmable option and related method' [patent_app_type] => utility [patent_app_number] => 10/709665 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478355.pdf [firstpage_image] =>[orig_patent_app_number] => 10709665 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709665
Input/output circuits with programmable option and related method May 20, 2004 Issued
Array ( [id] => 336989 [patent_doc_number] => 07509618 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method and apparatus for facilitating an adaptive electronic design automation tool' [patent_app_type] => utility [patent_app_number] => 10/844285 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5071 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509618.pdf [firstpage_image] =>[orig_patent_app_number] => 10844285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844285
Method and apparatus for facilitating an adaptive electronic design automation tool May 11, 2004 Issued
Array ( [id] => 801756 [patent_doc_number] => 07426704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling' [patent_app_type] => utility [patent_app_number] => 10/842085 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2840 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/426/07426704.pdf [firstpage_image] =>[orig_patent_app_number] => 10842085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/842085
Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling May 9, 2004 Issued
Array ( [id] => 7047179 [patent_doc_number] => 20050251774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Circuit design property storage and manipulation' [patent_app_type] => utility [patent_app_number] => 11/089575 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4214 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251774.pdf [firstpage_image] =>[orig_patent_app_number] => 11089575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089575
Circuit design property storage and manipulation May 6, 2004 Abandoned
Array ( [id] => 478746 [patent_doc_number] => 07231621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Speed verification of an embedded processor in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/837395 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6597 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231621.pdf [firstpage_image] =>[orig_patent_app_number] => 10837395 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/837395
Speed verification of an embedded processor in a programmable logic device Apr 29, 2004 Issued
Array ( [id] => 6927629 [patent_doc_number] => 20050240886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'METHOD OF PERFORMING DESIGN RULE CHECKING' [patent_app_type] => utility [patent_app_number] => 10/709205 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240886.pdf [firstpage_image] =>[orig_patent_app_number] => 10709205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709205
Method of performing latch up check on an integrated circuit design Apr 20, 2004 Issued
Array ( [id] => 610951 [patent_doc_number] => 07152217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Alleviating timing based congestion within circuit designs' [patent_app_type] => utility [patent_app_number] => 10/828895 [patent_app_country] => US [patent_app_date] => 2004-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3680 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/152/07152217.pdf [firstpage_image] =>[orig_patent_app_number] => 10828895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828895
Alleviating timing based congestion within circuit designs Apr 19, 2004 Issued
Array ( [id] => 563589 [patent_doc_number] => 07165233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Test ket layout for precisely monitoring 3-foil lens aberration effects' [patent_app_type] => utility [patent_app_number] => 10/709075 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165233.pdf [firstpage_image] =>[orig_patent_app_number] => 10709075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709075
Test ket layout for precisely monitoring 3-foil lens aberration effects Apr 11, 2004 Issued
Array ( [id] => 7174270 [patent_doc_number] => 20040201083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Hard-macro and semiconductor integrated circuit including the same' [patent_app_type] => new [patent_app_number] => 10/820755 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20040201083.pdf [firstpage_image] =>[orig_patent_app_number] => 10820755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820755
Hard-macro and semiconductor integrated circuit including the same Apr 8, 2004 Abandoned
Array ( [id] => 6954031 [patent_doc_number] => 20050229126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'IC layout physical verification method' [patent_app_type] => utility [patent_app_number] => 10/820365 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5135 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229126.pdf [firstpage_image] =>[orig_patent_app_number] => 10820365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820365
IC layout physical verification method Apr 6, 2004 Issued
Array ( [id] => 869162 [patent_doc_number] => 07370311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-06 [patent_title] => 'Generating components on a programmable device using a high-level language' [patent_app_type] => utility [patent_app_number] => 10/816685 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8279 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370311.pdf [firstpage_image] =>[orig_patent_app_number] => 10816685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816685
Generating components on a programmable device using a high-level language Mar 31, 2004 Issued
Array ( [id] => 6954038 [patent_doc_number] => 20050229133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method of designing a circuit of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/811835 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2426 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229133.pdf [firstpage_image] =>[orig_patent_app_number] => 10811835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/811835
Method of designing a circuit layout of a semiconductor device Mar 29, 2004 Issued
Array ( [id] => 6954050 [patent_doc_number] => 20050229145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method and system for chrome cut-out regions on a reticle' [patent_app_type] => utility [patent_app_number] => 10/812465 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2832 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229145.pdf [firstpage_image] =>[orig_patent_app_number] => 10812465 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812465
Method and system for chrome cut-out regions on a reticle Mar 28, 2004 Abandoned
Array ( [id] => 762265 [patent_doc_number] => 07020862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Circuits and methods for analyzing timing characteristics of sequential logic elements' [patent_app_type] => utility [patent_app_number] => 10/803335 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020862.pdf [firstpage_image] =>[orig_patent_app_number] => 10803335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/803335
Circuits and methods for analyzing timing characteristics of sequential logic elements Mar 16, 2004 Issued
Array ( [id] => 637712 [patent_doc_number] => 07131103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Conductor stack shifting' [patent_app_type] => utility [patent_app_number] => 10/793055 [patent_app_country] => US [patent_app_date] => 2004-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4258 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/131/07131103.pdf [firstpage_image] =>[orig_patent_app_number] => 10793055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793055
Conductor stack shifting Mar 3, 2004 Issued
Array ( [id] => 555059 [patent_doc_number] => 07174529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Acute angle avoidance during routing' [patent_app_type] => utility [patent_app_number] => 10/779954 [patent_app_country] => US [patent_app_date] => 2004-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9399 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174529.pdf [firstpage_image] =>[orig_patent_app_number] => 10779954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779954
Acute angle avoidance during routing Feb 13, 2004 Issued
Array ( [id] => 609708 [patent_doc_number] => 07155690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Method for co-verifying hardware and software for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/766955 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5218 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155690.pdf [firstpage_image] =>[orig_patent_app_number] => 10766955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766955
Method for co-verifying hardware and software for a semiconductor device Jan 29, 2004 Issued
Array ( [id] => 561417 [patent_doc_number] => 07178126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Method of protecting a semiconductor integrated circuit from plasma damage' [patent_app_type] => utility [patent_app_number] => 10/760295 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6598 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/178/07178126.pdf [firstpage_image] =>[orig_patent_app_number] => 10760295 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760295
Method of protecting a semiconductor integrated circuit from plasma damage Jan 20, 2004 Issued
Array ( [id] => 7042813 [patent_doc_number] => 20050160390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'CLONED AND ORIGINAL CIRCUIT SHAPE MERGING' [patent_app_type] => utility [patent_app_number] => 10/707845 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160390.pdf [firstpage_image] =>[orig_patent_app_number] => 10707845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707845
Cloned and original circuit shape merging Jan 15, 2004 Issued
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