
Yelena Rossoshek
Examiner (ID: 11381)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 1218 |
| Issued Applications | 1046 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7057483
[patent_doc_number] => 20050278658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Standard cell library having cell drive strengths selected according to delay'
[patent_app_type] => utility
[patent_app_number] => 10/856345
[patent_app_country] => US
[patent_app_date] => 2004-05-27
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[pdf_file] => publications/A1/0278/20050278658.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/856345 | Standard cell library having cell drive strengths selected according to delay | May 26, 2004 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Input/output circuits with programmable option and related method'
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Array
(
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[patent_issue_date] => 2009-03-24
[patent_title] => 'Method and apparatus for facilitating an adaptive electronic design automation tool'
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[patent_app_date] => 2004-05-12
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Array
(
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[patent_issue_date] => 2008-09-16
[patent_title] => 'Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling'
[patent_app_type] => utility
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Array
(
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[patent_doc_number] => 20050251774
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[patent_issue_date] => 2005-11-10
[patent_title] => 'Circuit design property storage and manipulation'
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Array
(
[id] => 478746
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[patent_issue_date] => 2007-06-12
[patent_title] => 'Speed verification of an embedded processor in a programmable logic device'
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Array
(
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[patent_doc_number] => 20050240886
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[patent_title] => 'METHOD OF PERFORMING DESIGN RULE CHECKING'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709205 | Method of performing latch up check on an integrated circuit design | Apr 20, 2004 | Issued |
Array
(
[id] => 610951
[patent_doc_number] => 07152217
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[patent_issue_date] => 2006-12-19
[patent_title] => 'Alleviating timing based congestion within circuit designs'
[patent_app_type] => utility
[patent_app_number] => 10/828895
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[pdf_file] => patents/07/152/07152217.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/828895 | Alleviating timing based congestion within circuit designs | Apr 19, 2004 | Issued |
Array
(
[id] => 563589
[patent_doc_number] => 07165233
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[patent_issue_date] => 2007-01-16
[patent_title] => 'Test ket layout for precisely monitoring 3-foil lens aberration effects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709075 | Test ket layout for precisely monitoring 3-foil lens aberration effects | Apr 11, 2004 | Issued |
Array
(
[id] => 7174270
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[patent_title] => 'Hard-macro and semiconductor integrated circuit including the same'
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Array
(
[id] => 6954031
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[patent_title] => 'IC layout physical verification method'
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Array
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[id] => 869162
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Array
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Array
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Array
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Array
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