
Yelena Rossoshek
Examiner (ID: 3705, Phone: (571)272-1905 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1218 |
| Issued Applications | 1047 |
| Pending Applications | 23 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14184191
[patent_doc_number] => 20190111800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => HIGH COVERAGE BATTERY USAGE MONITOR
[patent_app_type] => utility
[patent_app_number] => 16/160102
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160102
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/160102 | HIGH COVERAGE BATTERY USAGE MONITOR | Oct 14, 2018 | Abandoned |
Array
(
[id] => 13961667
[patent_doc_number] => 20190057178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-21
[patent_title] => INTEGRATED CIRCUIT LAYOUT WIRING FOR MULTI-CORE CHIPS
[patent_app_type] => utility
[patent_app_number] => 16/160780
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8791
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160780
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/160780 | Channel-less integrated circuit layout wiring for chips including a plurality of partitions | Oct 14, 2018 | Issued |
Array
(
[id] => 16638433
[patent_doc_number] => 10916955
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-09
[patent_title] => Modular multi-functional conference wearable system
[patent_app_type] => utility
[patent_app_number] => 16/158921
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 23
[patent_no_of_words] => 8020
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/158921 | Modular multi-functional conference wearable system | Oct 11, 2018 | Issued |
Array
(
[id] => 15689117
[patent_doc_number] => 20200099222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => CHIP POSITION SENSING FOR BATTERY PROTECTORS
[patent_app_type] => utility
[patent_app_number] => 16/159323
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159323
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159323 | Chip position sensing for battery protectors | Oct 11, 2018 | Issued |
Array
(
[id] => 14217705
[patent_doc_number] => 20190121237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => PREDICTIVE MODELING OF METROLOGY IN SEMICONDUCTOR PROCESSES
[patent_app_type] => utility
[patent_app_number] => 16/151035
[patent_app_country] => US
[patent_app_date] => 2018-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151035
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/151035 | Predictive modeling of metrology in semiconductor processes | Oct 2, 2018 | Issued |
Array
(
[id] => 16431872
[patent_doc_number] => 10831958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Integrated circuit design with optimized timing constraint configuration
[patent_app_type] => utility
[patent_app_number] => 16/143842
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3771
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143842
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143842 | Integrated circuit design with optimized timing constraint configuration | Sep 26, 2018 | Issued |
Array
(
[id] => 15715355
[patent_doc_number] => 20200104444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => Multi-Input Logic Circuitry
[patent_app_type] => utility
[patent_app_number] => 16/144688
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144688
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/144688 | Multi-input logic circuitry | Sep 26, 2018 | Issued |
Array
(
[id] => 16387227
[patent_doc_number] => 10812079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-20
[patent_title] => Integrated circuit layout wiring for multi-core chips
[patent_app_type] => utility
[patent_app_number] => 16/142627
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 12120
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142627
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/142627 | Integrated circuit layout wiring for multi-core chips | Sep 25, 2018 | Issued |
Array
(
[id] => 16145827
[patent_doc_number] => 10705984
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-07-07
[patent_title] => High-speed low VT drift receiver
[patent_app_type] => utility
[patent_app_number] => 16/143123
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9426
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143123
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143123 | High-speed low VT drift receiver | Sep 25, 2018 | Issued |
Array
(
[id] => 15691381
[patent_doc_number] => 20200100354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => AUTOMATIC DETERMINATION OF POWER PLANE SHAPE IN PRINTED CIRCUIT BOARD
[patent_app_type] => utility
[patent_app_number] => 16/140611
[patent_app_country] => US
[patent_app_date] => 2018-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4931
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140611
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140611 | Automatic determination of power plane shape in printed circuit board | Sep 24, 2018 | Issued |
Array
(
[id] => 13845867
[patent_doc_number] => 20190026418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRATED CIRCUIT DESIGNS
[patent_app_type] => utility
[patent_app_number] => 16/141379
[patent_app_country] => US
[patent_app_date] => 2018-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4295
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141379
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/141379 | Large cluster persistence during placement optimization of integrated circuit designs | Sep 24, 2018 | Issued |
Array
(
[id] => 16278107
[patent_doc_number] => 10761131
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-01
[patent_title] => Method for optimally connecting scan segments in two-dimensional compression chains
[patent_app_type] => utility
[patent_app_number] => 16/140701
[patent_app_country] => US
[patent_app_date] => 2018-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140701 | Method for optimally connecting scan segments in two-dimensional compression chains | Sep 24, 2018 | Issued |
Array
(
[id] => 15684425
[patent_doc_number] => 20200096876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => Dose Map Optimization for Mask Making
[patent_app_type] => utility
[patent_app_number] => 16/141197
[patent_app_country] => US
[patent_app_date] => 2018-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9067
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141197
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/141197 | Dose Map Optimization for Mask Making | Sep 24, 2018 | Abandoned |
Array
(
[id] => 16121357
[patent_doc_number] => 20200212701
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => METHOD FOR CONTROLLING MULTI-MODE CHARGING, MOBILE TERMINAL, AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 16/646590
[patent_app_country] => US
[patent_app_date] => 2018-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16646590
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/646590 | Method for controlling multi-mode charging, mobile terminal, and storage medium | Sep 12, 2018 | Issued |
Array
(
[id] => 14444243
[patent_doc_number] => 20190179995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => METHOD AND APPARATUS FOR DESIGNING INTERCONNECTION STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/100400
[patent_app_country] => US
[patent_app_date] => 2018-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100400
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/100400 | Method and apparatus for designing interconnection structure and method for manufacturing interconnection structure | Aug 9, 2018 | Issued |
Array
(
[id] => 16248569
[patent_doc_number] => 10747932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => Smart placement, visualization and optimization methodology for component placement and planning
[patent_app_type] => utility
[patent_app_number] => 16/100093
[patent_app_country] => US
[patent_app_date] => 2018-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8576
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/100093 | Smart placement, visualization and optimization methodology for component placement and planning | Aug 8, 2018 | Issued |
Array
(
[id] => 17591047
[patent_doc_number] => 11329327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-10
[patent_title] => Electricity storage system and management device
[patent_app_type] => utility
[patent_app_number] => 16/637923
[patent_app_country] => US
[patent_app_date] => 2018-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 9225
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16637923
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/637923 | Electricity storage system and management device | Aug 2, 2018 | Issued |
Array
(
[id] => 16807142
[patent_doc_number] => 20210129695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => A MOBILE CHARGING UNIT, PARTICULARLY FOR ELECTRIC VEHICLES, AND A MANAGEMENT SYSTEM THEREOF FOR THE DELIVERY OF CHARGES ON REQUEST
[patent_app_type] => utility
[patent_app_number] => 16/635727
[patent_app_country] => US
[patent_app_date] => 2018-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6118
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16635727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/635727 | Mobile charging unit, particularly for electric vehicles, and a management system thereof for the delivery of charges on request | Aug 1, 2018 | Issued |
Array
(
[id] => 18001428
[patent_doc_number] => 11502542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-15
[patent_title] => Multi-modular capacitive wireless power transfer circuit and related techniques
[patent_app_type] => utility
[patent_app_number] => 16/636211
[patent_app_country] => US
[patent_app_date] => 2018-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3062
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636211
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/636211 | Multi-modular capacitive wireless power transfer circuit and related techniques | Jul 31, 2018 | Issued |
Array
(
[id] => 16032499
[patent_doc_number] => 10678670
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Evaluating fairness in devices under test
[patent_app_type] => utility
[patent_app_number] => 16/046574
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8169
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046574
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/046574 | Evaluating fairness in devices under test | Jul 25, 2018 | Issued |