Search

Yelena Rossoshek

Examiner (ID: 11381)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1218
Issued Applications
1046
Pending Applications
23
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16032499 [patent_doc_number] => 10678670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Evaluating fairness in devices under test [patent_app_type] => utility [patent_app_number] => 16/046574 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046574 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046574
Evaluating fairness in devices under test Jul 25, 2018 Issued
Array ( [id] => 15982357 [patent_doc_number] => 10671506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Evaluating fairness in devices under test [patent_app_type] => utility [patent_app_number] => 16/046548 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046548
Evaluating fairness in devices under test Jul 25, 2018 Issued
Array ( [id] => 16971932 [patent_doc_number] => 11067902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Computational metrology [patent_app_type] => utility [patent_app_number] => 16/635584 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 30593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16635584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/635584
Computational metrology Jul 10, 2018 Issued
Array ( [id] => 14413961 [patent_doc_number] => 20190172824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/022965 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022965 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022965
Semiconductor device and method of manufacturing the same Jun 28, 2018 Issued
Array ( [id] => 13453101 [patent_doc_number] => 20180278093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => System and Method for Providing Wireless Power in a Removable Wireless Charging Module [patent_app_type] => utility [patent_app_number] => 15/993358 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993358 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993358
System and method for providing wireless power in a removable wireless charging module May 29, 2018 Issued
Array ( [id] => 16248563 [patent_doc_number] => 10747926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Low-power test compression for launch-on-capture transition fault testing [patent_app_type] => utility [patent_app_number] => 15/972599 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9758 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972599 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972599
Low-power test compression for launch-on-capture transition fault testing May 6, 2018 Issued
Array ( [id] => 16130569 [patent_doc_number] => 10699046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => System and method for achieving functional coverage closure for electronic system verification [patent_app_type] => utility [patent_app_number] => 15/972597 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7560 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972597 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972597
System and method for achieving functional coverage closure for electronic system verification May 6, 2018 Issued
Array ( [id] => 14523983 [patent_doc_number] => 10339254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Integrated circuit design systems and methods [patent_app_type] => utility [patent_app_number] => 15/966581 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966581 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966581
Integrated circuit design systems and methods Apr 29, 2018 Issued
Array ( [id] => 17194950 [patent_doc_number] => 11163707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Virtualization in hierarchical cortical emulation frameworks [patent_app_type] => utility [patent_app_number] => 15/959551 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959551
Virtualization in hierarchical cortical emulation frameworks Apr 22, 2018 Issued
Array ( [id] => 17046311 [patent_doc_number] => 11099487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method and apparatus for optimization of lithographic process [patent_app_type] => utility [patent_app_number] => 16/495416 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11690 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16495416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/495416
Method and apparatus for optimization of lithographic process Mar 27, 2018 Issued
Array ( [id] => 15855329 [patent_doc_number] => 10642951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Register pull-out for sequential circuit blocks in circuit designs [patent_app_type] => utility [patent_app_number] => 15/914579 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914579
Register pull-out for sequential circuit blocks in circuit designs Mar 6, 2018 Issued
Array ( [id] => 13417927 [patent_doc_number] => 20180260506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory [patent_app_type] => utility [patent_app_number] => 15/914072 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914072
Address generators for verifying integrated circuit hardware designs for cache memory Mar 6, 2018 Issued
Array ( [id] => 15889691 [patent_doc_number] => 10651201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration [patent_app_type] => utility [patent_app_number] => 15/913530 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 11473 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913530 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913530
Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration Mar 5, 2018 Issued
Array ( [id] => 16279226 [patent_doc_number] => 10762257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Equivalent circuit construction method, simulation method and simulation device [patent_app_type] => utility [patent_app_number] => 15/913096 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9422 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913096
Equivalent circuit construction method, simulation method and simulation device Mar 5, 2018 Issued
Array ( [id] => 15701589 [patent_doc_number] => 10606974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => System and method for dynamic visual guidance of mutually paired components in a circuit design editor [patent_app_type] => utility [patent_app_number] => 15/911421 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8325 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911421
System and method for dynamic visual guidance of mutually paired components in a circuit design editor Mar 4, 2018 Issued
Array ( [id] => 16065813 [patent_doc_number] => 10691859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Integrated circuit and method of designing layout of integrated circuit [patent_app_type] => utility [patent_app_number] => 15/908291 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 27196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908291
Integrated circuit and method of designing layout of integrated circuit Feb 27, 2018 Issued
Array ( [id] => 13420981 [patent_doc_number] => 20180262033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => VIRAL DISTRIBUTION OF BATTERY MANAGEMENT PARAMETERS [patent_app_type] => utility [patent_app_number] => 15/890035 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890035
Viral distribution of battery management parameters Feb 5, 2018 Issued
Array ( [id] => 16534774 [patent_doc_number] => 10877370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Stretchable layout design for EUV defect mitigation [patent_app_type] => utility [patent_app_number] => 15/882235 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882235 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882235
Stretchable layout design for EUV defect mitigation Jan 28, 2018 Issued
Array ( [id] => 16323324 [patent_doc_number] => 10783290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => IC manufacturing recipe similarity evaluation methods and systems [patent_app_type] => utility [patent_app_number] => 15/882138 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9868 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882138
IC manufacturing recipe similarity evaluation methods and systems Jan 28, 2018 Issued
Array ( [id] => 13611603 [patent_doc_number] => 20180357351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => CELL PLACEMENT SITE OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/882288 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882288 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882288
Cell placement site optimization Jan 28, 2018 Issued
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