Yelena Rossoshek

Array ( [id] => 15517491 [patent_doc_number] => 10565334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-18 [patent_title] => Targeted delay optimization through programmable clock delays [patent_app_type] => utility [patent_app_number] => 15/849216 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14473415 [patent_doc_number] => 20190188352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 15/848556 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12838882 [patent_doc_number] => 20180171467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium [patent_app_type] => utility [patent_app_number] => 15/849271 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15953453 [patent_doc_number] => 10664636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Pin number definition based analytics [patent_app_type] => utility [patent_app_number] => 15/848945 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15855457 [patent_doc_number] => 10643016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design [patent_app_type] => utility [patent_app_number] => 15/846540 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12892795 [patent_doc_number] => 20180189440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DESIGN SUPPORT APPARATUS, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT PROGRAM [patent_app_type] => utility [patent_app_number] => 15/846277 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13556981 [patent_doc_number] => 20180330038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => INTEGRATED CIRCUIT IDENTIFICATION AND REVERSE ENGINEERING [patent_app_type] => utility [patent_app_number] => 15/842639 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17325238 [patent_doc_number] => 11216250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks [patent_app_type] => utility [patent_app_number] => 15/833287 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15671119 [patent_doc_number] => 10599792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Circuit design analyzer [patent_app_type] => utility [patent_app_number] => 15/822668 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 14359 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15473361 [patent_doc_number] => 10552559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Glitch-aware phase algebra for clock analysis [patent_app_type] => utility [patent_app_number] => 15/818144 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 14325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15639267 [patent_doc_number] => 10592627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Optimizing integrated circuit designs based on interactions between multiple integration design rules [patent_app_type] => utility [patent_app_number] => 15/816210 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9530 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15241047 [patent_doc_number] => 20190375309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => TEMPERATURE-MONITORED CHARGING SYSTEM FOR TRANSMITTING ELECTRIC CHARGE CURRENTS [patent_app_type] => utility [patent_app_number] => 16/341546 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16341546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12802504 [patent_doc_number] => 20180159338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SYSTEMS AND METHODS FOR WIRELESSLY DELIVERING POWER TO ELECTRONIC DEVICES IN RESPONSE TO COMMANDS RECEIVED AT A WIRELESS POWER TRANSMITTER [patent_app_type] => utility [patent_app_number] => 15/729574 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14298771 [patent_doc_number] => 10289512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Persistent command parameter table for pre-silicon device testing [patent_app_type] => utility [patent_app_number] => 15/724902 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4678 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 517 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14107781 [patent_doc_number] => 20190095566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => METHOD OF REPORTING CIRCUIT PERFORMANCE FOR HIGH-LEVEL SYNTHESIS [patent_app_type] => utility [patent_app_number] => 15/715795 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15232275 [patent_doc_number] => 10503862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Electronic circuit design editor with off-screen violation display and correction [patent_app_type] => utility [patent_app_number] => 15/714044 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15789635 [patent_doc_number] => 10628544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Optimizing integrated circuit designs based on interactions between multiple integration design rules [patent_app_type] => utility [patent_app_number] => 15/714086 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9533 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15106905 [patent_doc_number] => 10474779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Bisection methodology for on-chip variation tolerant clock signal distribution in an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/713305 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12592572 [patent_doc_number] => 20180089353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Virtual Terminals for Linear-Parameter Extraction [patent_app_type] => utility [patent_app_number] => 15/713506 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14539747 [patent_doc_number] => 20190205495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHOD AND SYSTEM FOR FABRICATING UNIQUE CHIPS USING A CHARGED PARTICLE MULTI-BEAMLET LITHOGRAPHY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/331538 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16331538 [rel_patent_id] =>[rel_patent_doc_number] =>)