| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 18857620
[patent_doc_number] => 11855217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer
[patent_app_type] => utility
[patent_app_number] => 17/120814
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8422
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120814
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/120814 | Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer | Dec 13, 2020 | Issued |
Array
(
[id] => 17615653
[patent_doc_number] => 20220157933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/118630
[patent_app_country] => US
[patent_app_date] => 2020-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3808
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118630
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118630 | Semiconductor device with a single diffusion break structure having a sidewall aligned with a gate sidewall | Dec 10, 2020 | Issued |
Array
(
[id] => 16781819
[patent_doc_number] => 20210118898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/113285
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113285
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/113285 | Semiconductor memory device including integrated control circuit and solid-state drive controller | Dec 6, 2020 | Issued |
Array
(
[id] => 16781737
[patent_doc_number] => 20210118816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => Dummy Fin Etch to Form Recesses in Substrate
[patent_app_type] => utility
[patent_app_number] => 17/112029
[patent_app_country] => US
[patent_app_date] => 2020-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4869
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112029
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/112029 | Method for forming recesses in a substrate by etching dummy fins | Dec 3, 2020 | Issued |
Array
(
[id] => 16715795
[patent_doc_number] => 20210082942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 17/106414
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106414
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/106414 | Semiconductor device having a pad proximate to a step structure section of an array chip | Nov 29, 2020 | Issued |
Array
(
[id] => 17232552
[patent_doc_number] => 20210359109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 17/101291
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14062
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101291
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/101291 | Semiconductor device having a corner spacer | Nov 22, 2020 | Issued |
Array
(
[id] => 18387435
[patent_doc_number] => 11658230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Method for forming a semiconductor structure including plasma cleaning operations
[patent_app_type] => utility
[patent_app_number] => 17/101546
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 6623
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101546
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/101546 | Method for forming a semiconductor structure including plasma cleaning operations | Nov 22, 2020 | Issued |
Array
(
[id] => 17925882
[patent_doc_number] => 11469144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Semiconductor arrangement with fin features having different heights
[patent_app_type] => utility
[patent_app_number] => 17/098786
[patent_app_country] => US
[patent_app_date] => 2020-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 3529
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098786
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098786 | Semiconductor arrangement with fin features having different heights | Nov 15, 2020 | Issued |
Array
(
[id] => 18357862
[patent_doc_number] => 11646268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-09
[patent_title] => Semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing liner having different thicknesses
[patent_app_type] => utility
[patent_app_number] => 17/097876
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 10396
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097876
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/097876 | Semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing liner having different thicknesses | Nov 12, 2020 | Issued |
Array
(
[id] => 18688480
[patent_doc_number] => 11784226
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Semiconductor gate-all-around device having an anti-punch-through (APT) layer including carbon
[patent_app_type] => utility
[patent_app_number] => 17/097945
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7967
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097945
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/097945 | Semiconductor gate-all-around device having an anti-punch-through (APT) layer including carbon | Nov 12, 2020 | Issued |
Array
(
[id] => 17615656
[patent_doc_number] => 20220157936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => ISOLATION LAYERS FOR STACKED TRANSISTOR STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/097959
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097959
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/097959 | Methods for manufacturing isolation layers in stacked transistor structures | Nov 12, 2020 | Issued |
Array
(
[id] => 18874889
[patent_doc_number] => 11862712
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases
[patent_app_type] => utility
[patent_app_number] => 16/949728
[patent_app_country] => US
[patent_app_date] => 2020-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 10852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949728
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/949728 | Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases | Nov 11, 2020 | Issued |
Array
(
[id] => 17295419
[patent_doc_number] => 20210391258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/095169
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17916
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095169
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/095169 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE | Nov 10, 2020 | Abandoned |
Array
(
[id] => 18047969
[patent_doc_number] => 11521927
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => Buried power rail for scaled vertical transport field effect transistor
[patent_app_type] => utility
[patent_app_number] => 17/093683
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093683
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/093683 | Buried power rail for scaled vertical transport field effect transistor | Nov 9, 2020 | Issued |
Array
(
[id] => 16765450
[patent_doc_number] => 20210111032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => FABRICATION OF FINS USING VARIABLE SPACERS
[patent_app_type] => utility
[patent_app_number] => 17/087185
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5421
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087185
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/087185 | Method of fabricating semiconductor fins by differentially oxidizing mandrel sidewalls | Nov 1, 2020 | Issued |
Array
(
[id] => 17583260
[patent_doc_number] => 20220140115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => Metal Gate Patterning Process and Devices Thereof
[patent_app_type] => utility
[patent_app_number] => 17/087131
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6950
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087131
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/087131 | Metal gate patterning process including dielectric Fin formation | Nov 1, 2020 | Issued |
Array
(
[id] => 18105535
[patent_doc_number] => 11545432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-03
[patent_title] => Semiconductor device with source and drain vias having different sizes
[patent_app_type] => utility
[patent_app_number] => 17/083976
[patent_app_country] => US
[patent_app_date] => 2020-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 11232
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083976
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/083976 | Semiconductor device with source and drain vias having different sizes | Oct 28, 2020 | Issued |
Array
(
[id] => 17668508
[patent_doc_number] => 11362213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-14
[patent_title] => Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench
[patent_app_type] => utility
[patent_app_number] => 17/081894
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 83
[patent_no_of_words] => 11072
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081894
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081894 | Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench | Oct 26, 2020 | Issued |
Array
(
[id] => 19094065
[patent_doc_number] => 11955532
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
[patent_app_type] => utility
[patent_app_number] => 17/080713
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 121
[patent_figures_cnt] => 224
[patent_no_of_words] => 73821
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080713
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080713 | Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric | Oct 25, 2020 | Issued |
Array
(
[id] => 17188902
[patent_doc_number] => 20210335787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/078274
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078274
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078274 | Method of manufacturing a semiconductor device by patterning a serpentine cut pattern | Oct 22, 2020 | Issued |