| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 16904870
[patent_doc_number] => 20210183786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-17
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/940933
[patent_app_country] => US
[patent_app_date] => 2020-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11474
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940933
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/940933 | Semiconductor device having interconnection lines with different linewidths and metal patterns | Jul 27, 2020 | Issued |
Array
(
[id] => 17389657
[patent_doc_number] => 20220037509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => Spacer Structure For Nano-Sheet-Based Devices
[patent_app_type] => utility
[patent_app_number] => 16/941504
[patent_app_country] => US
[patent_app_date] => 2020-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15067
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941504
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/941504 | Methods of forming nano-sheet-based devices having inner spacer structures with different widths | Jul 27, 2020 | Issued |
Array
(
[id] => 16440589
[patent_doc_number] => 20200357916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 16/940117
[patent_app_country] => US
[patent_app_date] => 2020-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4107
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940117
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/940117 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS | Jul 26, 2020 | Pending |
Array
(
[id] => 17716551
[patent_doc_number] => 11380549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Semiconductor device with a work function layer having a concentration of fluorine
[patent_app_type] => utility
[patent_app_number] => 16/939364
[patent_app_country] => US
[patent_app_date] => 2020-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 11772
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939364
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/939364 | Semiconductor device with a work function layer having a concentration of fluorine | Jul 26, 2020 | Issued |
Array
(
[id] => 17174372
[patent_doc_number] => 20210328043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => Selective Removal of Gate Dielectric from Dummy Fin
[patent_app_type] => utility
[patent_app_number] => 16/939943
[patent_app_country] => US
[patent_app_date] => 2020-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939943
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/939943 | Method for selective removal of gate dielectric from dummy fin | Jul 26, 2020 | Issued |
Array
(
[id] => 16995601
[patent_doc_number] => 20210234021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-29
[patent_title] => LATERALLY ETCHED SPACERS FOR SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/937389
[patent_app_country] => US
[patent_app_date] => 2020-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8660
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937389
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/937389 | Method for laterally etching gate spacers | Jul 22, 2020 | Issued |
Array
(
[id] => 17373821
[patent_doc_number] => 20220028873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => NON-VOLATILE MEMORY CELL ARRAYS WITH A SECTIONED ACTIVE REGION
[patent_app_type] => utility
[patent_app_number] => 16/935691
[patent_app_country] => US
[patent_app_date] => 2020-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935691
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/935691 | Non-volatile memory cell arrays with a sectioned active region and methods of manufacturing thereof | Jul 21, 2020 | Issued |
Array
(
[id] => 18767077
[patent_doc_number] => 11817491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-14
[patent_title] => Semiconductor device having an air gap along a gate spacer
[patent_app_type] => utility
[patent_app_number] => 16/935061
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 61
[patent_figures_cnt] => 61
[patent_no_of_words] => 14660
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935061
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/935061 | Semiconductor device having an air gap along a gate spacer | Jul 20, 2020 | Issued |
Array
(
[id] => 17359842
[patent_doc_number] => 20220020638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => Interconnect Structures with Selective Barrier for BEOL Applications
[patent_app_type] => utility
[patent_app_number] => 16/932193
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4870
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932193
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/932193 | Interconnect Structures with Selective Barrier for BEOL Applications | Jul 16, 2020 | Abandoned |
Array
(
[id] => 16677711
[patent_doc_number] => 20210066477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => Multi-Gate Devices And Method Of Fabrication Thereof
[patent_app_type] => utility
[patent_app_number] => 16/931930
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8156
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931930
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931930 | Method of manufacturing a source/drain feature in a multi-gate semiconductor structure | Jul 16, 2020 | Issued |
Array
(
[id] => 17070852
[patent_doc_number] => 20210273069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-02
[patent_title] => TRANSISTOR DEVICE WITH RECESSED GATE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/929640
[patent_app_country] => US
[patent_app_date] => 2020-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8500
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929640
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/929640 | Transistor device with a gate structure having recesses overlying an interface between isolation and device regions | Jul 14, 2020 | Issued |
Array
(
[id] => 17347122
[patent_doc_number] => 20220013453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => Method for Manufacturing an Anchor-Shaped Backside Via
[patent_app_type] => utility
[patent_app_number] => 16/926447
[patent_app_country] => US
[patent_app_date] => 2020-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10226
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926447
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/926447 | Method for manufacturing an anchor-shaped backside via | Jul 9, 2020 | Issued |
Array
(
[id] => 17956334
[patent_doc_number] => 11482447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-25
[patent_title] => Method of forming an integrated chip having a cavity between metal features
[patent_app_type] => utility
[patent_app_number] => 16/923424
[patent_app_country] => US
[patent_app_date] => 2020-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 7435
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923424
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/923424 | Method of forming an integrated chip having a cavity between metal features | Jul 7, 2020 | Issued |
Array
(
[id] => 17893400
[patent_doc_number] => 11456384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-27
[patent_title] => Fin-based laterally diffused structure having a gate with two adjacent metal layers and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/921068
[patent_app_country] => US
[patent_app_date] => 2020-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5131
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921068
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/921068 | Fin-based laterally diffused structure having a gate with two adjacent metal layers and method for manufacturing the same | Jul 5, 2020 | Issued |
Array
(
[id] => 18840159
[patent_doc_number] => 11848238
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Methods for manufacturing semiconductor devices with tunable low-k inner air spacers
[patent_app_type] => utility
[patent_app_number] => 16/916397
[patent_app_country] => US
[patent_app_date] => 2020-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8409
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916397
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/916397 | Methods for manufacturing semiconductor devices with tunable low-k inner air spacers | Jun 29, 2020 | Issued |
Array
(
[id] => 16888973
[patent_doc_number] => 20210175170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/910748
[patent_app_country] => US
[patent_app_date] => 2020-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910748
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/910748 | Semiconductor device with stacked wirings having respective pitches and ratios therebetween | Jun 23, 2020 | Issued |
Array
(
[id] => 18001089
[patent_doc_number] => 11502200
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-15
[patent_title] => Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material
[patent_app_type] => utility
[patent_app_number] => 16/906490
[patent_app_country] => US
[patent_app_date] => 2020-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5254
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906490
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/906490 | Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material | Jun 18, 2020 | Issued |
Array
(
[id] => 17295616
[patent_doc_number] => 20210391455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/901680
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901680
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/901680 | Methods of forming a semiconductor device with a gate structure having a dielectric protection layer | Jun 14, 2020 | Issued |
Array
(
[id] => 17295615
[patent_doc_number] => 20210391454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => SOURCE AND DRAIN EPITAXIAL LAYERS
[patent_app_type] => utility
[patent_app_number] => 16/901603
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6030
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901603
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/901603 | Method of manufacturing a facet-free source/drain epitaxial structure having an amorphous or polycrystalline layer | Jun 14, 2020 | Issued |
Array
(
[id] => 16715610
[patent_doc_number] => 20210082757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/898906
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898906
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/898906 | Method of manufacturing a semiconductor device having a source/drain contact plug with a recessed portion using a mask pattern layer | Jun 10, 2020 | Issued |