Younes Boulghassoul

Array ( [id] => 15688501 [patent_doc_number] => 20200098914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => DEPLETED FIN TRANSISTOR AND METHOD OF FABRICATING [patent_app_type] => utility [patent_app_number] => 16/137148 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14110407 [patent_doc_number] => 20190096879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/137524 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16308761 [patent_doc_number] => 10777571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Three-dimensional semiconductor device having a peripheral connection plug in a through region below a gate stack structure [patent_app_type] => utility [patent_app_number] => 16/137079 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 66 [patent_no_of_words] => 14308 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15547793 [patent_doc_number] => 10573688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Magnetic junction device having an inter-layer stack between a hard magnetic layer and a reference layer, and associated magnetic random access memory [patent_app_type] => utility [patent_app_number] => 16/137336 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6339 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746497 [patent_doc_number] => 10971498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Method of forming a semiconductor memory device with a laterally etched bottom dielectric layer [patent_app_type] => utility [patent_app_number] => 16/137513 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4433 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13740789 [patent_doc_number] => 20180374864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/121123 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14801249 [patent_doc_number] => 10403635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Semiconductor memory device having bonding metal between an array chip and a circuit chip [patent_app_type] => utility [patent_app_number] => 16/106639 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6299 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14542945 [patent_doc_number] => 20190207094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Three-Dimensional Magnetic Memory Devices with Buffer Layers [patent_app_type] => utility [patent_app_number] => 16/103835 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15375993 [patent_doc_number] => 10529724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures [patent_app_type] => utility [patent_app_number] => 16/056660 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 11525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13582103 [patent_doc_number] => 20180342600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK [patent_app_type] => utility [patent_app_number] => 16/055401 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13613513 [patent_doc_number] => 20180358306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => Dummy Fin Etch to Form Recesses in Substrate [patent_app_type] => utility [patent_app_number] => 16/045298 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13543053 [patent_doc_number] => 20180323073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => FABRICATION OF FINS USING VARIABLE SPACERS [patent_app_type] => utility [patent_app_number] => 16/040093 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15985139 [patent_doc_number] => 10672909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Strained gate semiconductor device having an interlayer dielectric doped with oxygen and a large species material [patent_app_type] => utility [patent_app_number] => 16/022686 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17152595 [patent_doc_number] => 11145686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Semiconductor photodetector device with protection against ambient back light [patent_app_type] => utility [patent_app_number] => 16/621140 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16621140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218453 [patent_doc_number] => 20190371913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INVERTED T-SHAPED METAL GATE BETWEEN INNER SPACERS [patent_app_type] => utility [patent_app_number] => 15/991454 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16410121 [patent_doc_number] => 10818687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Three-dimensional semiconductor memory device with vertical structures penetrating a dummy insulating pattern in a connection region [patent_app_type] => utility [patent_app_number] => 15/991476 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12958 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218227 [patent_doc_number] => 20190371800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ANTENNA DIODES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/991268 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13598627 [patent_doc_number] => 20180350862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => IMAGING DEVICE AND CAMERA SYSTEM [patent_app_type] => utility [patent_app_number] => 15/991676 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218217 [patent_doc_number] => 20190371795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks using an Etch Barrier [patent_app_type] => utility [patent_app_number] => 15/991184 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16386660 [patent_doc_number] => 10811505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Gate electrode having upper and lower capping patterns [patent_app_type] => utility [patent_app_number] => 15/990983 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9394 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990983 [rel_patent_id] =>[rel_patent_doc_number] =>)