Search

Younes Boulghassoul

Examiner (ID: 6342, Phone: (571)270-5514 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
629
Issued Applications
512
Pending Applications
76
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15217933 [patent_doc_number] => 20190371653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION CAP AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/991523 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991523
Method of manufacturing an integrated inductor with protections caps on conductive lines May 28, 2018 Issued
Array ( [id] => 13785317 [patent_doc_number] => 20190006197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => WAFER PART AND CHIP PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/991374 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991374
WAFER PART AND CHIP PACKAGING METHOD May 28, 2018 Abandoned
Array ( [id] => 14050067 [patent_doc_number] => 20190081141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS [patent_app_type] => utility [patent_app_number] => 15/988453 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988453
Scalable circuit-under-pad device topologies for lateral GaN power transistors May 23, 2018 Issued
Array ( [id] => 16202091 [patent_doc_number] => 10727271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Memory device having source contacts located at intersections of linear portions of a common source, electronic systems, and associated methods [patent_app_type] => utility [patent_app_number] => 15/982251 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 8871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982251
Memory device having source contacts located at intersections of linear portions of a common source, electronic systems, and associated methods May 16, 2018 Issued
Array ( [id] => 15250229 [patent_doc_number] => 10510643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Semiconductor package with lead frame and recessed solder terminals [patent_app_type] => utility [patent_app_number] => 15/978497 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978497
Semiconductor package with lead frame and recessed solder terminals May 13, 2018 Issued
Array ( [id] => 13378479 [patent_doc_number] => 20180240781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => Three-Dimensional Package Structure and the Method to Fabricate Thereof [patent_app_type] => utility [patent_app_number] => 15/961865 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15961865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/961865
Three-dimensional (3D) package structure having an epoxy molding compound layer between a discrete inductor and an encapsulating connecting structure Apr 23, 2018 Issued
Array ( [id] => 15376081 [patent_doc_number] => 10529769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Method of manufacturing a color image sensor having an optically sensitive material with multiple thicknesses [patent_app_type] => utility [patent_app_number] => 15/953459 [patent_app_country] => US [patent_app_date] => 2018-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 18451 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15953459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/953459
Method of manufacturing a color image sensor having an optically sensitive material with multiple thicknesses Apr 14, 2018 Issued
Array ( [id] => 14301039 [patent_doc_number] => 10290651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor devices with non-overlapping slits in-between memory blocks [patent_app_type] => utility [patent_app_number] => 15/937430 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 7588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937430
Semiconductor devices with non-overlapping slits in-between memory blocks Mar 26, 2018 Issued
Array ( [id] => 17590800 [patent_doc_number] => 11329077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Semiconductor device with a through electrode reception part wider than a through electrode, solid-state imaging device, and electronic equipment [patent_app_type] => utility [patent_app_number] => 16/496773 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 10564 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496773
Semiconductor device with a through electrode reception part wider than a through electrode, solid-state imaging device, and electronic equipment Mar 15, 2018 Issued
Array ( [id] => 13420127 [patent_doc_number] => 20180261606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/909419 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909419
Fabrication method of a semiconductor structure by a gate cutting process with multiple sidewall spacers formation in a dummy gate opening Feb 28, 2018 Issued
Array ( [id] => 13420291 [patent_doc_number] => 20180261688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/909285 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909285
Method for manufacturing FinFETs by implanting counter-doped regions in lightly-doped S/D extensions away from the channel Feb 28, 2018 Issued
Array ( [id] => 16148195 [patent_doc_number] => 10707174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Semiconductor device having lithography marks and resin portions in a cutting region [patent_app_type] => utility [patent_app_number] => 15/909425 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 5606 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909425 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909425
Semiconductor device having lithography marks and resin portions in a cutting region Feb 28, 2018 Issued
Array ( [id] => 15580679 [patent_doc_number] => 10580733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Integrated circuit having heterogeneous source/drain and gate contacts [patent_app_type] => utility [patent_app_number] => 15/909212 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9954 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909212
Integrated circuit having heterogeneous source/drain and gate contacts Feb 28, 2018 Issued
Array ( [id] => 16148231 [patent_doc_number] => 10707193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Semiconductor device package having a mounting plate with protrusions exposed from a resin material [patent_app_type] => utility [patent_app_number] => 15/909428 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 8007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909428
Semiconductor device package having a mounting plate with protrusions exposed from a resin material Feb 28, 2018 Issued
Array ( [id] => 14367291 [patent_doc_number] => 10304960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Vertical transistor with multi-doping S/D regions [patent_app_type] => utility [patent_app_number] => 15/909348 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 6143 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909348
Vertical transistor with multi-doping S/D regions Feb 28, 2018 Issued
Array ( [id] => 15283711 [patent_doc_number] => 10514516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Semiconductor optical device monolithically integrating optical waveguides with photodiodes having a shared bias pad and apparatus implementing the same [patent_app_type] => utility [patent_app_number] => 15/909235 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5596 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909235 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909235
Semiconductor optical device monolithically integrating optical waveguides with photodiodes having a shared bias pad and apparatus implementing the same Feb 28, 2018 Issued
Array ( [id] => 14785135 [patent_doc_number] => 20190267465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/907214 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907214
Method of manufacturing a protective stack on a semiconductor fin Feb 26, 2018 Issued
Array ( [id] => 13893815 [patent_doc_number] => 10199463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires [patent_app_type] => utility [patent_app_number] => 15/906355 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3631 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906355
Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires Feb 26, 2018 Issued
Array ( [id] => 13405619 [patent_doc_number] => 20180254352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/904867 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904867
Semiconductor device having an oxide layer with a concentration gradient of oxygen and an insulating layer with excess oxygen Feb 25, 2018 Issued
Array ( [id] => 15218499 [patent_doc_number] => 20190371936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER [patent_app_type] => utility [patent_app_number] => 16/477119 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/477119
Silicon carbide semiconductor device having a conductive layer formed above a bottom surface of a well region so as not to be in ohmic connection with the well region and power converter including the same Feb 21, 2018 Issued
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