Search

Younes Boulghassoul

Examiner (ID: 6070, Phone: (571)270-5514 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
628
Issued Applications
511
Pending Applications
78
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19821097 [patent_doc_number] => 20250079304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => SEMICONDUCTOR GAP FILL AND PLANARIZATION [patent_app_type] => utility [patent_app_number] => 18/457975 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457975
SEMICONDUCTOR GAP FILL AND PLANARIZATION Aug 28, 2023 Pending
Array ( [id] => 19788526 [patent_doc_number] => 20250062205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SHIELDED THROUGH SUBSTRATE VIA STRUCTURES FOR A SILICON INTERCONNECT DIE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/451043 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451043
SHIELDED THROUGH SUBSTRATE VIA STRUCTURES FOR A SILICON INTERCONNECT DIE AND METHODS OF FORMING THE SAME Aug 15, 2023 Pending
Array ( [id] => 20509049 [patent_doc_number] => 12543341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Transistor structure having a charge storage layer arranged between a field plate and a drift region [patent_app_type] => utility [patent_app_number] => 18/449712 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449712
Transistor structure having a charge storage layer arranged between a field plate and a drift region Aug 14, 2023 Issued
Array ( [id] => 19741368 [patent_doc_number] => 12218216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method for manufacturing semiconductor devices having gate spacers with bottom portions recessed in a fin [patent_app_type] => utility [patent_app_number] => 18/232191 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 6565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232191 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232191
Method for manufacturing semiconductor devices having gate spacers with bottom portions recessed in a fin Aug 8, 2023 Issued
Array ( [id] => 19040404 [patent_doc_number] => 20240090219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/231284 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231284
VERTICAL MEMORY DEVICE Aug 7, 2023 Pending
Array ( [id] => 18812788 [patent_doc_number] => 20230387125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/362862 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362862 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362862
Semiconductor device having air spacers Jul 30, 2023 Issued
Array ( [id] => 18789564 [patent_doc_number] => 20230378257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ISOLATION LAYERS FOR STACKED TRANSISTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/361574 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361574
ISOLATION LAYERS FOR STACKED TRANSISTOR STRUCTURES Jul 27, 2023 Pending
Array ( [id] => 18812875 [patent_doc_number] => 20230387212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Semiconductor Gate-All-Around Device [patent_app_type] => utility [patent_app_number] => 18/360080 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360080
Semiconductor gate-all-around structure having carbon-doped anti-punch-through (APT) layers over wells Jul 26, 2023 Issued
Array ( [id] => 18774663 [patent_doc_number] => 20230369494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/357797 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357797
FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME Jul 23, 2023 Pending
Array ( [id] => 19269390 [patent_doc_number] => 20240213094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SELF-ALIGNED LINE-AND-VIA STRUCTURE AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/355029 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355029
SELF-ALIGNED LINE-AND-VIA STRUCTURE AND METHOD OF MAKING THE SAME Jul 18, 2023 Pending
Array ( [id] => 19712735 [patent_doc_number] => 20250022877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SPACERS [patent_app_type] => utility [patent_app_number] => 18/350933 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350933
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SPACERS Jul 11, 2023 Pending
Array ( [id] => 19606823 [patent_doc_number] => 20240397703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/220290 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220290
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 10, 2023 Pending
Array ( [id] => 18898648 [patent_doc_number] => 20240014133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION [patent_app_type] => utility [patent_app_number] => 18/343127 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343127
STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION Jun 27, 2023 Pending
Array ( [id] => 20418375 [patent_doc_number] => 12501680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Method for manufacturing a metal gate by a gate replacement process including carbon Ion implantation of a zero interlayer dielectric [patent_app_type] => utility [patent_app_number] => 18/341083 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341083
Method for manufacturing a metal gate by a gate replacement process including carbon Ion implantation of a zero interlayer dielectric Jun 25, 2023 Issued
Array ( [id] => 18680062 [patent_doc_number] => 20230317720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/207065 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207065
Planar buried channel structure integrated with non-planar structures Jun 6, 2023 Issued
Array ( [id] => 20205597 [patent_doc_number] => 12408393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor device with a single diffusion break structure and a gate structure having aligned sidewalls [patent_app_type] => utility [patent_app_number] => 18/206618 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206618 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206618
Semiconductor device with a single diffusion break structure and a gate structure having aligned sidewalls Jun 6, 2023 Issued
Array ( [id] => 19900325 [patent_doc_number] => 12278265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Method for fabricating a fin with minimal length between two single-diffusion break (SDB) trenches [patent_app_type] => utility [patent_app_number] => 18/206617 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206617
Method for fabricating a fin with minimal length between two single-diffusion break (SDB) trenches Jun 6, 2023 Issued
Array ( [id] => 18743512 [patent_doc_number] => 20230352500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Solid-State Image Sensing Device with a Capacitance Switching Transistor Overlapping a Photodiode and Electronic Device Having the Same [patent_app_type] => utility [patent_app_number] => 18/330061 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330061
Solid-State Image Sensing Device with a Capacitance Switching Transistor Overlapping a Photodiode and Electronic Device Having the Same Jun 5, 2023 Abandoned
Array ( [id] => 19619419 [patent_doc_number] => 20240405099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => OPTIMIZED FIN HEIGHT FOR FINFET TRANSISTOR AND METHOD OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 18/327628 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327628
OPTIMIZED FIN HEIGHT FOR FINFET TRANSISTOR AND METHOD OF FABRICATING THEREOF May 31, 2023 Pending
Array ( [id] => 19349427 [patent_doc_number] => 20240258391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/323323 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323323
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE May 23, 2023 Pending
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