Search

Younes Boulghassoul

Examiner (ID: 6342, Phone: (571)270-5514 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
629
Issued Applications
512
Pending Applications
76
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18669986 [patent_doc_number] => 11776898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Sidewall interconnect metallization structures for integrated circuit devices [patent_app_type] => utility [patent_app_number] => 16/955722 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9654 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16955722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/955722
Sidewall interconnect metallization structures for integrated circuit devices Feb 21, 2018 Issued
Array ( [id] => 14722475 [patent_doc_number] => 20190252301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/897833 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897833
Power device having a substrate with metal layers exposed at surfaces of an insulation layer and manufacturing method thereof Feb 14, 2018 Issued
Array ( [id] => 12849223 [patent_doc_number] => 20180174914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => MULTI-DEPTH ETCHING IN SEMICONDUCTOR ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 15/892444 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/892444
Semiconductor arrangement with fins having multiple heights and a dielectric layer recessed in the substrate Feb 8, 2018 Issued
Array ( [id] => 14429667 [patent_doc_number] => 10319647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Semiconductor structure with overlapping fins having different directions, and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/890001 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 4276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890001
Semiconductor structure with overlapping fins having different directions, and methods of fabricating the same Feb 5, 2018 Issued
Array ( [id] => 13909213 [patent_doc_number] => 20190043811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SIGNAL ISOLATION FOR MODULE WITH BALL GRID ARRAY [patent_app_type] => utility [patent_app_number] => 15/883294 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883294
Packaged module having a ball grid array with grounding shielding pins for electromagnetic isolation, method of manufacturing the same, and wireless device comprising the same Jan 29, 2018 Issued
Array ( [id] => 15286465 [patent_doc_number] => 10515902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures [patent_app_type] => utility [patent_app_number] => 15/871919 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871919
Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures Jan 14, 2018 Issued
Array ( [id] => 12896776 [patent_doc_number] => 20180190767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/859042 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859042 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859042
High-voltage semiconductor device having a doped isolation region between a level shift region and a high voltage region Dec 28, 2017 Issued
Array ( [id] => 12896764 [patent_doc_number] => 20180190763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => HIGH-VOLTAGE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/859050 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859050
HIGH-VOLTAGE SEMICONDUCTOR DEVICE Dec 28, 2017 Abandoned
Array ( [id] => 14542297 [patent_doc_number] => 20190206770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => INTEGRATED CIRCUIT PACKAGE WITH LEAD LOCK [patent_app_type] => utility [patent_app_number] => 15/858643 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858643
INTEGRATED CIRCUIT PACKAGE WITH LEAD LOCK Dec 28, 2017 Abandoned
Array ( [id] => 14542925 [patent_doc_number] => 20190207084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Spin Hall Effect (SHE) Assisted Three-Dimensional Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) [patent_app_type] => utility [patent_app_number] => 15/858808 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858808
Spin hall effect (SHE) assisted three-dimensional spin transfer torque magnetic random access memory (STT-MRAM) Dec 28, 2017 Issued
Array ( [id] => 16553164 [patent_doc_number] => 10886330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch [patent_app_type] => utility [patent_app_number] => 15/859150 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7473 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859150
Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch Dec 28, 2017 Issued
Array ( [id] => 14672459 [patent_doc_number] => 10374153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Method for manufacturing a magnetic memory device by pre-patterning a bottom electrode prior to patterning a magnetic material [patent_app_type] => utility [patent_app_number] => 15/859171 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5043 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859171
Method for manufacturing a magnetic memory device by pre-patterning a bottom electrode prior to patterning a magnetic material Dec 28, 2017 Issued
Array ( [id] => 14534125 [patent_doc_number] => 20190202684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => PROTECTIVE BONDLINE CONTROL STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/859184 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859184
PROTECTIVE BONDLINE CONTROL STRUCTURE Dec 28, 2017 Abandoned
Array ( [id] => 14543921 [patent_doc_number] => 20190207582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => 3D PRINTING OF PROTECTIVE SHELL STRUCTURES FOR STRESS SENSITIVE CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/858892 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858892
3D-printed protective shell structures for stress sensitive circuits Dec 28, 2017 Issued
Array ( [id] => 15250353 [patent_doc_number] => 10510705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Semiconductor package structure having a second encapsulant extending in a cavity defined by a first encapsulant [patent_app_type] => utility [patent_app_number] => 15/858714 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 57 [patent_no_of_words] => 19497 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858714
Semiconductor package structure having a second encapsulant extending in a cavity defined by a first encapsulant Dec 28, 2017 Issued
Array ( [id] => 14644771 [patent_doc_number] => 10367136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Methods for manufacturing a perpendicular magnetic tunnel junction (p-MTJ) MRAM having a precessional spin current injection (PSC) structure [patent_app_type] => utility [patent_app_number] => 15/859162 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4238 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859162 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859162
Methods for manufacturing a perpendicular magnetic tunnel junction (p-MTJ) MRAM having a precessional spin current injection (PSC) structure Dec 28, 2017 Issued
Array ( [id] => 15376241 [patent_doc_number] => 10529849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => High-voltage semiconductor device including a super-junction doped structure [patent_app_type] => utility [patent_app_number] => 15/858792 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9181 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858792
High-voltage semiconductor device including a super-junction doped structure Dec 28, 2017 Issued
Array ( [id] => 14541685 [patent_doc_number] => 20190206464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Multi-Layer Magnetic Memory Devices [patent_app_type] => utility [patent_app_number] => 15/859157 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859157
Magnetic tunnel junction (MTJ) memory device having a composite free magnetic layer Dec 28, 2017 Issued
Array ( [id] => 14603697 [patent_doc_number] => 10355046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-16 [patent_title] => Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) [patent_app_type] => utility [patent_app_number] => 15/859139 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9949 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859139
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) Dec 28, 2017 Issued
Array ( [id] => 14542239 [patent_doc_number] => 20190206741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHOD AND STRUCTURE TO ELIMINATE SUBSTRATE COUPLING IN COMMON DRAIN DEVICES [patent_app_type] => utility [patent_app_number] => 15/858862 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858862
METHOD AND STRUCTURE TO ELIMINATE SUBSTRATE COUPLING IN COMMON DRAIN DEVICES Dec 28, 2017 Abandoned
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