| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 18008511
[patent_doc_number] => 20220367278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => TUNABLE LOW-K INNER AIR SPACERS OF SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/815388
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8448
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815388
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815388 | Semiconductor devices with tunable low-K inner air spacers | Jul 26, 2022 | Issued |
Array
(
[id] => 19654606
[patent_doc_number] => 12176407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within
[patent_app_type] => utility
[patent_app_number] => 17/874486
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 36
[patent_no_of_words] => 8577
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874486 | Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within | Jul 26, 2022 | Issued |
Array
(
[id] => 18008922
[patent_doc_number] => 20220367689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => METAL GATE PATTERNING PROCESS AND DEVICES THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/875194
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6977
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875194
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/875194 | Device having a gate electrode wrapping around semiconductor layers and proximate to a dielectric fin | Jul 26, 2022 | Issued |
Array
(
[id] => 19597003
[patent_doc_number] => 12154856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-26
[patent_title] => Methods of manufacturing via structures on source/drain contacts
[patent_app_type] => utility
[patent_app_number] => 17/873782
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 11237
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873782
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873782 | Methods of manufacturing via structures on source/drain contacts | Jul 25, 2022 | Issued |
Array
(
[id] => 19842852
[patent_doc_number] => 12255255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Method of manufacturing a FinFET with merged epitaxial source/drain regions
[patent_app_type] => utility
[patent_app_number] => 17/815020
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 35
[patent_no_of_words] => 11743
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815020
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815020 | Method of manufacturing a FinFET with merged epitaxial source/drain regions | Jul 25, 2022 | Issued |
Array
(
[id] => 18008866
[patent_doc_number] => 20220367633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/874171
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874171 | SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICES | Jul 25, 2022 | Pending |
Array
(
[id] => 18008902
[patent_doc_number] => 20220367669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => Air Spacers For Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 17/873771
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873771
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873771 | Methods for forming air spacers in semiconductor devices | Jul 25, 2022 | Issued |
Array
(
[id] => 19582682
[patent_doc_number] => 12148812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Nano-sheet-based devices having inner spacer structures or gate portions with variable dimensions
[patent_app_type] => utility
[patent_app_number] => 17/814952
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 41
[patent_no_of_words] => 15096
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814952
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814952 | Nano-sheet-based devices having inner spacer structures or gate portions with variable dimensions | Jul 25, 2022 | Issued |
Array
(
[id] => 17993674
[patent_doc_number] => 20220359711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Semiconductor Devices and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/873830
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10490
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873830
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873830 | Method of manufacturing a semiconductor device having insulation fin structures | Jul 25, 2022 | Issued |
Array
(
[id] => 19654614
[patent_doc_number] => 12176415
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Device with a dummy fin contacting a gate isolation region
[patent_app_type] => utility
[patent_app_number] => 17/814756
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 57
[patent_figures_cnt] => 69
[patent_no_of_words] => 8490
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814756
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814756 | Device with a dummy fin contacting a gate isolation region | Jul 24, 2022 | Issued |
Array
(
[id] => 17993694
[patent_doc_number] => 20220359731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Multi-Gate Devices And Method Of Fabrication Thereof
[patent_app_type] => utility
[patent_app_number] => 17/870292
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870292
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870292 | Multi-gate devices having a semiconductor layer between an inner spacer and an epitaxial feature | Jul 20, 2022 | Issued |
Array
(
[id] => 19671051
[patent_doc_number] => 12183823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Fin field-effect transistor with a gate structure having a dielectric protection layer
[patent_app_type] => utility
[patent_app_number] => 17/868999
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8331
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868999
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/868999 | Fin field-effect transistor with a gate structure having a dielectric protection layer | Jul 19, 2022 | Issued |
Array
(
[id] => 17993170
[patent_doc_number] => 20220359207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Fin Field-Effect Transistor Device and Method of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/869057
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11475
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869057
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/869057 | FinFET device having a gate with a tapering bottom portion and a gate fill material with a widening bottom portion | Jul 19, 2022 | Issued |
Array
(
[id] => 19494396
[patent_doc_number] => 12113120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Gate electrode having a work-function layer including materials with different average grain sizes
[patent_app_type] => utility
[patent_app_number] => 17/813814
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 25
[patent_no_of_words] => 7943
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813814
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/813814 | Gate electrode having a work-function layer including materials with different average grain sizes | Jul 19, 2022 | Issued |
Array
(
[id] => 17993718
[patent_doc_number] => 20220359755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => FINFET DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/813888
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12497
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813888
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/813888 | Method of manufacturing a FinFET by implanting a dielectric with a dopant | Jul 19, 2022 | Issued |
Array
(
[id] => 17986316
[patent_doc_number] => 20220352353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => EPITAXIAL FEATURES OF SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/869704
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869704
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/869704 | Semiconductor device with phosphorus-doped epitaxial features | Jul 19, 2022 | Issued |
Array
(
[id] => 19733899
[patent_doc_number] => 12211901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Semiconductor device having a doped fin well
[patent_app_type] => utility
[patent_app_number] => 17/869321
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 35
[patent_no_of_words] => 9883
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869321
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/869321 | Semiconductor device having a doped fin well | Jul 19, 2022 | Issued |
Array
(
[id] => 20274823
[patent_doc_number] => 12444608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Structure having gate spacers with projecting portions extending into a gate dielectric
[patent_app_type] => utility
[patent_app_number] => 17/863006
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 5927
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863006
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/863006 | Structure having gate spacers with projecting portions extending into a gate dielectric | Jul 11, 2022 | Issued |
Array
(
[id] => 19741290
[patent_doc_number] => 12218136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith
[patent_app_type] => utility
[patent_app_number] => 17/861565
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6336
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861565
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/861565 | Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith | Jul 10, 2022 | Issued |
Array
(
[id] => 18258416
[patent_doc_number] => 20230085456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/859472
[patent_app_country] => US
[patent_app_date] => 2022-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8567
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859472
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/859472 | Semiconductor device having conductive portions in a groove and contacting a gate insulating layer | Jul 6, 2022 | Issued |