Search

Younes Boulghassoul

Examiner (ID: 6070, Phone: (571)270-5514 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
628
Issued Applications
511
Pending Applications
78
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17933132 [patent_doc_number] => 20220328258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMS SWITCH INCLUDING AN EMBEDDED METAL CONTACT [patent_app_type] => utility [patent_app_number] => 17/715213 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715213
Method for manufacturing a MEMS switch having an embedded metal contact Apr 6, 2022 Issued
Array ( [id] => 17723385 [patent_doc_number] => 20220216107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/701275 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701275
Semiconductor device having a source/drain contact plug with an upwardly protruding portion Mar 21, 2022 Issued
Array ( [id] => 17676825 [patent_doc_number] => 20220189992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/689898 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689898
Three-dimensional memory devices having backside insulating structures and methods for forming the same Mar 7, 2022 Issued
Array ( [id] => 17840794 [patent_doc_number] => 20220278100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Structure and Method for MOSFET Device [patent_app_type] => utility [patent_app_number] => 17/681236 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/681236
Fin-based device having an isolation gate interfacing with a source/drain Feb 24, 2022 Issued
Array ( [id] => 17630867 [patent_doc_number] => 20220165882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => STRAINED GATE SEMICONDUCTOR DEVICE WITH DOPED INTERLAYER DIELECTRIC MATERIAL [patent_app_type] => utility [patent_app_number] => 17/669317 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669317
Strained gate semiconductor device having an interlayer dielectric doped with large species material Feb 9, 2022 Issued
Array ( [id] => 17615456 [patent_doc_number] => 20220157736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SEMICONDUCTOR DEVICE HAVING INTERCONNECTION LINES WITH DIFFERENT LINEWIDTHS AND METAL PATTERNS [patent_app_type] => utility [patent_app_number] => 17/590238 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590238
Semiconductor device having interconnection lines with different linewidths and metal patterns Jan 31, 2022 Issued
Array ( [id] => 18125986 [patent_doc_number] => 20230011605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/590359 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590359
Metal-insulator-metal (MIM) capacitor with a top electrode having an oxygen-enriched portion Jan 31, 2022 Issued
Array ( [id] => 19919763 [patent_doc_number] => 12295159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Superjunction semiconductor device with different effective epitaxial layer thicknesses [patent_app_type] => utility [patent_app_number] => 17/584832 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584832
Superjunction semiconductor device with different effective epitaxial layer thicknesses Jan 25, 2022 Issued
Array ( [id] => 19294590 [patent_doc_number] => 12033954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Packaged module with ball grid array and grounding pins for signal isolation, method of manufacturing the same, and wireless device comprising the same [patent_app_type] => utility [patent_app_number] => 17/582915 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582915
Packaged module with ball grid array and grounding pins for signal isolation, method of manufacturing the same, and wireless device comprising the same Jan 23, 2022 Issued
Array ( [id] => 18317554 [patent_doc_number] => 11631638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Semiconductor structure having an anchor-shaped backside via [patent_app_type] => utility [patent_app_number] => 17/582314 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 40 [patent_no_of_words] => 10252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582314
Semiconductor structure having an anchor-shaped backside via Jan 23, 2022 Issued
Array ( [id] => 18704747 [patent_doc_number] => 11791264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method for preparing semiconductor device including conductive contact having tapering profile [patent_app_type] => utility [patent_app_number] => 17/580948 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6877 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580948
Method for preparing semiconductor device including conductive contact having tapering profile Jan 20, 2022 Issued
Array ( [id] => 17582918 [patent_doc_number] => 20220139773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SELF-ALIGNED BARRIER FOR METAL VIAS [patent_app_type] => utility [patent_app_number] => 17/575444 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575444
Self-aligned barrier for metal vias Jan 12, 2022 Issued
Array ( [id] => 19229656 [patent_doc_number] => 12009300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Wiring structures having intersecting metal patterns [patent_app_type] => utility [patent_app_number] => 17/569774 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 16705 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569774
Wiring structures having intersecting metal patterns Jan 5, 2022 Issued
Array ( [id] => 17900932 [patent_doc_number] => 20220310594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/569363 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569363
Semiconductor device having an isolation structure between adjacent source/drain regions Jan 4, 2022 Issued
Array ( [id] => 20360140 [patent_doc_number] => 12476145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Self-aligned cut-metal layer method [patent_app_type] => utility [patent_app_number] => 17/559813 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 48 [patent_no_of_words] => 3305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559813
Self-aligned cut-metal layer method Dec 21, 2021 Issued
Array ( [id] => 17486155 [patent_doc_number] => 20220093659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SOLID-STATE IMAGE SENSING DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/541509 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541509
Solid-state image sensing device with a capacitance switching transistor overlapping a photodiode and electronic device having the same Dec 2, 2021 Issued
Array ( [id] => 19123546 [patent_doc_number] => 11967540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Integrated circuit direct cooling systems having substrates in contact with a cooling medium [patent_app_type] => utility [patent_app_number] => 17/457100 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 39 [patent_no_of_words] => 6622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457100
Integrated circuit direct cooling systems having substrates in contact with a cooling medium Nov 30, 2021 Issued
Array ( [id] => 20361746 [patent_doc_number] => 12477764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes [patent_app_type] => utility [patent_app_number] => 17/529394 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 45 [patent_no_of_words] => 5426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529394
Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes Nov 17, 2021 Issued
Array ( [id] => 18723342 [patent_doc_number] => 11800720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory cell having a top electrode interconnect arranged laterally from a recess [patent_app_type] => utility [patent_app_number] => 17/528611 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528611
Memory cell having a top electrode interconnect arranged laterally from a recess Nov 16, 2021 Issued
Array ( [id] => 17431841 [patent_doc_number] => 20220059550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY CELL WITH OFFSET INTERCONNECT VIA [patent_app_type] => utility [patent_app_number] => 17/519808 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519808
MEMORY CELL WITH OFFSET INTERCONNECT VIA Nov 4, 2021 Pending
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