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Young Whang

Examiner (ID: 5243)

Most Active Art Unit
2103
Art Unit(s)
2103
Total Applications
382
Issued Applications
354
Pending Applications
5
Abandoned Applications
23

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19711367 [patent_doc_number] => 20250021509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SCALING PERFORMANCE IN A STORAGE SERVER WITH STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/896533 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896533
SCALING PERFORMANCE IN A STORAGE SERVER WITH STORAGE DEVICES Sep 24, 2024 Pending
Array ( [id] => 19834345 [patent_doc_number] => 20250086131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/825615 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/825615
METHOD AND SYSTEM Sep 4, 2024 Pending
Array ( [id] => 19834342 [patent_doc_number] => 20250086128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => MULTI-INTERFACE APPARATUS [patent_app_type] => utility [patent_app_number] => 18/820657 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820657
MULTI-INTERFACE APPARATUS Aug 29, 2024 Pending
Array ( [id] => 20447097 [patent_doc_number] => 20260003819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => METHOD AND DEVICE FOR CONFIGURING HOST SYSTEM,APPARATUS, COMPUTING SYSTEM, AND NONTRANSITORY READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/117007 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19117007 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/117007
METHOD AND DEVICE FOR CONFIGURING HOST SYSTEM,APPARATUS, COMPUTING SYSTEM, AND NONTRANSITORY READABLE STORAGE MEDIUM Aug 19, 2024 Pending
Array ( [id] => 19617072 [patent_doc_number] => 20240402752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory [patent_app_type] => utility [patent_app_number] => 18/802114 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802114
Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory Aug 12, 2024 Pending
Array ( [id] => 19617570 [patent_doc_number] => 20240403250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => PIN DETERMINATION FOR SINGLE-CONDUCTOR INTERFACE SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/799884 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/799884
Pin determination for single-conductor interface systems and methods Aug 8, 2024 Issued
Array ( [id] => 19617570 [patent_doc_number] => 20240403250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => PIN DETERMINATION FOR SINGLE-CONDUCTOR INTERFACE SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/799884 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/799884
Pin determination for single-conductor interface systems and methods Aug 8, 2024 Issued
Array ( [id] => 19892038 [patent_doc_number] => 20250117350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => PVT COMPENSATED SLOW TRANSITION SERIAL INTERFACE IO TRANSMITTER WITH REDUCED DELAY [patent_app_type] => utility [patent_app_number] => 18/788862 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788862 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788862
PVT COMPENSATED SLOW TRANSITION SERIAL INTERFACE IO TRANSMITTER WITH REDUCED DELAY Jul 29, 2024 Pending
Array ( [id] => 19711360 [patent_doc_number] => 20250021502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => BUS SLAVE DEVICE AND INTERRUPT REQUEST DETERMINATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/770307 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770307
BUS SLAVE DEVICE AND INTERRUPT REQUEST DETERMINATION METHOD THEREOF Jul 10, 2024 Pending
Array ( [id] => 19711360 [patent_doc_number] => 20250021502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => BUS SLAVE DEVICE AND INTERRUPT REQUEST DETERMINATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/770307 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770307
BUS SLAVE DEVICE AND INTERRUPT REQUEST DETERMINATION METHOD THEREOF Jul 10, 2024 Pending
Array ( [id] => 19711359 [patent_doc_number] => 20250021501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => ELECTROMECHANICAL SWITCHES ON INPUT/OUTPUT (I/O) COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/767645 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767645
ELECTROMECHANICAL SWITCHES ON INPUT/OUTPUT (I/O) COMPONENTS Jul 8, 2024 Pending
Array ( [id] => 19499197 [patent_doc_number] => 20240338215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/745042 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745042
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME Jun 16, 2024 Pending
Array ( [id] => 20215125 [patent_doc_number] => 12411778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Advanced initialization bus (AIB) [patent_app_type] => utility [patent_app_number] => 18/677623 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677623
Advanced initialization bus (AIB) May 28, 2024 Issued
Array ( [id] => 20380577 [patent_doc_number] => 20250363070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PRECISION TIMING ACROSS PCIe CEM NICS [patent_app_type] => utility [patent_app_number] => 18/672974 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672974
PRECISION TIMING ACROSS PCIe CEM NICS May 22, 2024 Pending
Array ( [id] => 19617572 [patent_doc_number] => 20240403252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/672994 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672994
INTEGRATED CIRCUIT May 22, 2024 Pending
Array ( [id] => 19633264 [patent_doc_number] => 20240411713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => TRANSMISSION MODULE FOR A TRANSMITTING/RECEIVING DEVICE OF A SUBSCRIBER STATION OF A SERIAL BUS SYSTEM, AND METHOD FOR TRANSMITTING A MESSAGE WITH DIFFERENTIAL SIGNALS IN A SERIAL BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 18/670968 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670968
Transmission module for a transmitting/receiving device of a subscriber station of a serial bus system, and method for transmitting a message with differential signals in a serial bus system May 21, 2024 Issued
Array ( [id] => 19978803 [patent_doc_number] => 12346278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Transport component authentication [patent_app_type] => utility [patent_app_number] => 18/664968 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664968
Transport component authentication May 14, 2024 Issued
Array ( [id] => 19420012 [patent_doc_number] => 20240296135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => BASE MODULE OF A NETWORK ASSEMBLY AND METHOD FOR CONFIGURING AN EXTENSION MODULE OF THE NETWORK ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/664956 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664956
BASE MODULE OF A NETWORK ASSEMBLY AND METHOD FOR CONFIGURING AN EXTENSION MODULE OF THE NETWORK ASSEMBLY May 14, 2024 Pending
Array ( [id] => 19320300 [patent_doc_number] => 20240241844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Method and System for Integrating Buffer Views into Buffer Access Operations in Reconfigurable Computing Environments [patent_app_type] => utility [patent_app_number] => 18/623180 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623180
Method and system for integrating buffer views into buffer access operations in reconfigurable computing environments Mar 31, 2024 Issued
Array ( [id] => 19514288 [patent_doc_number] => 20240345974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => ELECTRONIC DEVICE FOR PERFORMING COMMUNICATIONS WITH MASTER DEVICE BY SERIAL COMMUNICATIONS BUS AND METHOD FOR PERFORMING ASSIGNMENT OF IDENTIFIER ON ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/624092 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624092 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624092
ELECTRONIC DEVICE FOR PERFORMING COMMUNICATIONS WITH MASTER DEVICE BY SERIAL COMMUNICATIONS BUS AND METHOD FOR PERFORMING ASSIGNMENT OF IDENTIFIER ON ELECTRONIC DEVICE Mar 31, 2024 Pending
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