Young Whang

Array ( [id] => 19748012 [patent_doc_number] => 20250036577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SYSTEM AND METHOD TO FACILITATE ACCESS BY A REMOTE COMPUTER TO A PCIE CONFIGURATION SPACE [patent_app_type] => utility [patent_app_number] => 18/470051 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20145701 [patent_doc_number] => 12380044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor device, bus control circuit and bus control method [patent_app_type] => utility [patent_app_number] => 18/468032 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4608 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18864338 [patent_doc_number] => 20230418774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INTEGRATED CIRCUIT, CHIP, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/467379 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19802656 [patent_doc_number] => 20250068581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => Passive Clock Synchronization For Timing [patent_app_type] => utility [patent_app_number] => 18/237171 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819660 [patent_doc_number] => 20230394000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => INTERCONNECTION SYSTEM, DATA TRANSMISSION METHOD, AND CHIP [patent_app_type] => utility [patent_app_number] => 18/453733 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819660 [patent_doc_number] => 20230394000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => INTERCONNECTION SYSTEM, DATA TRANSMISSION METHOD, AND CHIP [patent_app_type] => utility [patent_app_number] => 18/453733 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18957486 [patent_doc_number] => 20240045813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY [patent_app_type] => utility [patent_app_number] => 18/236272 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19828067 [patent_doc_number] => 12248851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-11 [patent_title] => Thermalization and attenuation of signals within quantum computing systems via directional couplers [patent_app_type] => utility [patent_app_number] => 18/450996 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19911539 [patent_doc_number] => 12287748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection [patent_app_type] => utility [patent_app_number] => 18/446501 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19911539 [patent_doc_number] => 12287748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection [patent_app_type] => utility [patent_app_number] => 18/446501 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19911537 [patent_doc_number] => 12287746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Management of endpoint devices utilizing tag bridge devices [patent_app_type] => utility [patent_app_number] => 18/366019 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19857009 [patent_doc_number] => 12259845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Managing communications between chassis [patent_app_type] => utility [patent_app_number] => 18/230884 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6067 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881050 [patent_doc_number] => 20240004419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory [patent_app_type] => utility [patent_app_number] => 18/230418 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18941730 [patent_doc_number] => 20240036869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => HARDWARE STATE REPORTING USING INTERRUPT PINS [patent_app_type] => utility [patent_app_number] => 18/221230 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881456 [patent_doc_number] => 20240004825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SERIAL DAISY-CHAINED BUS POWER FOR SERIAL DAISY-CHAINED COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/346214 [patent_app_country] => US [patent_app_date] => 2023-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18714166 [patent_doc_number] => 20230336806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DISPLAY APPARATUS AND PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/340512 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660649 [patent_doc_number] => 20240427714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/338070 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660649 [patent_doc_number] => 20240427714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/338070 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19645093 [patent_doc_number] => 20240419613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND POWER CONSUMPTION IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/337235 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19645093 [patent_doc_number] => 20240419613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND POWER CONSUMPTION IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/337235 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337235 [rel_patent_id] =>[rel_patent_doc_number] =>)