Search

Younghuie Jessica Han

Examiner (ID: 17008, Phone: (571)272-2078 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2111, 2845, 2896, 2102, 2838
Total Applications
1804
Issued Applications
1646
Pending Applications
48
Abandoned Applications
111

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11791124 [patent_doc_number] => 09400751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Counter-based wide fetch management' [patent_app_type] => utility [patent_app_number] => 14/483576 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7040 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483576
Counter-based wide fetch management Sep 10, 2014 Issued
Array ( [id] => 10408846 [patent_doc_number] => 20150293855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'PAGE TABLE INCLUDING DATA FETCH WIDTH INDICATOR' [patent_app_type] => utility [patent_app_number] => 14/483550 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10210 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483550
Page table including data fetch width indicator Sep 10, 2014 Issued
Array ( [id] => 10948507 [patent_doc_number] => 20140351528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'BALANCING STORAGE UNIT UTILIZATION WITHIN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 14/458969 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 28868 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458969 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458969
Balancing storage unit utilization within a dispersed storage network Aug 12, 2014 Issued
Array ( [id] => 10681371 [patent_doc_number] => 20160027516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'EFFICIENT MODIFICATION OF DATA IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/339737 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339737 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/339737
EFFICIENT MODIFICATION OF DATA IN NON-VOLATILE MEMORY Jul 23, 2014 Abandoned
Array ( [id] => 12039524 [patent_doc_number] => 09817759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Multi-core CPU system for adjusting L2 cache character, method thereof, and devices having the same' [patent_app_type] => utility [patent_app_number] => 14/340215 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4354 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340215
Multi-core CPU system for adjusting L2 cache character, method thereof, and devices having the same Jul 23, 2014 Issued
Array ( [id] => 14330901 [patent_doc_number] => 10296469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Access control in a flash storage system [patent_app_type] => utility [patent_app_number] => 14/340169 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340169
Access control in a flash storage system Jul 23, 2014 Issued
Array ( [id] => 9840878 [patent_doc_number] => 20150032961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'System and Methods of Data Migration Between Storage Devices' [patent_app_type] => utility [patent_app_number] => 14/339201 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/339201
System and Methods of Data Migration Between Storage Devices Jul 22, 2014 Abandoned
Array ( [id] => 10258048 [patent_doc_number] => 20150143045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'CACHE CONTROL APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/253466 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3013 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253466
CACHE CONTROL APPARATUS AND METHOD Apr 14, 2014 Abandoned
Array ( [id] => 11258280 [patent_doc_number] => 09483179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Memory-area property storage including data fetch width indicator' [patent_app_type] => utility [patent_app_number] => 14/253072 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10026 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253072
Memory-area property storage including data fetch width indicator Apr 14, 2014 Issued
Array ( [id] => 11306410 [patent_doc_number] => 09513805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Page table including data fetch width indicator' [patent_app_type] => utility [patent_app_number] => 14/253059 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10175 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253059
Page table including data fetch width indicator Apr 14, 2014 Issued
Array ( [id] => 11179742 [patent_doc_number] => 09411735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Counter-based wide fetch management' [patent_app_type] => utility [patent_app_number] => 14/253086 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7004 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253086
Counter-based wide fetch management Apr 14, 2014 Issued
Array ( [id] => 11465592 [patent_doc_number] => 09582223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Efficient reclamation of pre-allocated direct memory access (DMA) memory' [patent_app_type] => utility [patent_app_number] => 14/252146 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7318 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252146 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252146
Efficient reclamation of pre-allocated direct memory access (DMA) memory Apr 13, 2014 Issued
Array ( [id] => 9386124 [patent_doc_number] => 20140089607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/077156 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6681 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077156
Input/output traffic backpressure prediction Nov 10, 2013 Issued
Array ( [id] => 10651227 [patent_doc_number] => 09367479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Management of destage tasks with large number of ranks' [patent_app_type] => utility [patent_app_number] => 14/074076 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4672 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074076
Management of destage tasks with large number of ranks Nov 6, 2013 Issued
Array ( [id] => 10651218 [patent_doc_number] => 09367470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Bounded cache searches' [patent_app_type] => utility [patent_app_number] => 14/070216 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8298 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/070216
Bounded cache searches Oct 31, 2013 Issued
Array ( [id] => 10236042 [patent_doc_number] => 20150121035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'Systems and Methods for Implementing Low-Latency Lookup Circuits Using Sparse Hash Functions' [patent_app_type] => utility [patent_app_number] => 14/069255 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 32839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069255
Systems and methods for implementing low-latency lookup circuits using sparse hash functions Oct 30, 2013 Issued
Array ( [id] => 10236040 [patent_doc_number] => 20150121034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'Systems and Methods for Implementing Low-Latency Lookup Circuits Using Multiple Hash Functions' [patent_app_type] => utility [patent_app_number] => 14/069253 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 22543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069253
Systems and methods for implementing low-latency lookup circuits using multiple hash functions Oct 30, 2013 Issued
Array ( [id] => 11806528 [patent_doc_number] => 09547597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Selection of post-request action based on combined response and input from the request source' [patent_app_type] => utility [patent_app_number] => 14/036195 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14731 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036195 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036195
Selection of post-request action based on combined response and input from the request source Sep 24, 2013 Issued
Array ( [id] => 10603112 [patent_doc_number] => 09323676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Non-data inclusive coherent (NIC) directory for cache' [patent_app_type] => utility [patent_app_number] => 13/784958 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784958
Non-data inclusive coherent (NIC) directory for cache Mar 4, 2013 Issued
Array ( [id] => 9017340 [patent_doc_number] => 20130232304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'ACCELERATED INTERLEAVED MEMORY DATA TRANSFERS IN MICROPROCESSOR-BASED SYSTEMS, AND RELATED DEVICES, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 13/784088 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10696 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784088
ACCELERATED INTERLEAVED MEMORY DATA TRANSFERS IN MICROPROCESSOR-BASED SYSTEMS, AND RELATED DEVICES, METHODS, AND COMPUTER-READABLE MEDIA Mar 3, 2013 Abandoned
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