Search

Yu-hsi David Sun

Examiner (ID: 17238)

Most Active Art Unit
2895
Art Unit(s)
2817, 2895, 4183
Total Applications
1196
Issued Applications
920
Pending Applications
80
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14110473 [patent_doc_number] => 20190096912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/003752 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003752
Array substrate and display device Jun 7, 2018 Issued
Array ( [id] => 15921991 [patent_doc_number] => 10658243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Method for forming replacement metal gate and related structures [patent_app_type] => utility [patent_app_number] => 16/002385 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8818 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16002385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/002385
Method for forming replacement metal gate and related structures Jun 6, 2018 Issued
Array ( [id] => 13452191 [patent_doc_number] => 20180277638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/988661 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988661
Semiconductor device May 23, 2018 Issued
Array ( [id] => 15077615 [patent_doc_number] => 10468306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Method for fabricating a row of MOS transistors [patent_app_type] => utility [patent_app_number] => 15/942540 [patent_app_country] => US [patent_app_date] => 2018-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4441 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942540 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942540
Method for fabricating a row of MOS transistors Mar 31, 2018 Issued
Array ( [id] => 14859671 [patent_doc_number] => 10418572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Flexible display device with bend stress reduction member and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 15/933326 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 20428 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933326
Flexible display device with bend stress reduction member and manufacturing method for the same Mar 21, 2018 Issued
Array ( [id] => 15138811 [patent_doc_number] => 10482887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Machine learning model assisted enhancement of audio and/or visual communications [patent_app_type] => utility [patent_app_number] => 15/925451 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/925451
Machine learning model assisted enhancement of audio and/or visual communications Mar 18, 2018 Issued
Array ( [id] => 16098641 [patent_doc_number] => 20200203307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => WIRE BONDING APPARATUS AND MANUFACTURING METHOD FOR SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/622291 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/622291
Wire bonding apparatus and manufacturing method for semiconductor apparatus Mar 13, 2018 Issued
Array ( [id] => 14800593 [patent_doc_number] => 10403304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Neural networks for identifying the potential of digitized audio to induce frisson in listeners [patent_app_type] => utility [patent_app_number] => 15/920283 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8841 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920283
Neural networks for identifying the potential of digitized audio to induce frisson in listeners Mar 12, 2018 Issued
Array ( [id] => 13304481 [patent_doc_number] => 20180203777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => Method of Phase Calibration for Double Data Rate Memory Interface and Related System [patent_app_type] => utility [patent_app_number] => 15/919137 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919137
Method of phase calibration for double data rate memory interface and related system Mar 11, 2018 Issued
Array ( [id] => 15462625 [patent_doc_number] => 20200044137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHOD FOR THE IN SITU PRODUCTION OF MAJORANA MATERIAL SUPERCONDUCTOR HYBRID NETWORKS AND TO A HYBRID STRUCTURE WHICH IS PRODUCED USING THE METHOD [patent_app_type] => utility [patent_app_number] => 16/486848 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486848
Method for the in situ production of Majorana material superconductor hybrid networks and to a hybrid structure which is produced using the method Feb 28, 2018 Issued
Array ( [id] => 15533045 [patent_doc_number] => 20200058828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => AlInN FILM, TWO-DIMENSIONAL PHOTONIC CRYSTAL RESONATOR, METHOD FOR MANUFACTURING THESE, AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 16/486556 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486556
AlInN film, two-dimensional photonic crystal resonator, method for manufacturing these, and semiconductor light-emitting element Feb 25, 2018 Issued
Array ( [id] => 16716079 [patent_doc_number] => 20210083226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, APPARATUS FOR MANUFACTURING A DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/961445 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961445
Display device, method of manufacturing display device, apparatus for manufacturing a display device Jan 17, 2018 Issued
Array ( [id] => 17166369 [patent_doc_number] => 11152482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Antiferroelectric gate dielectric transistors and their methods of fabrication [patent_app_type] => utility [patent_app_number] => 16/649933 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 10548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649933
Antiferroelectric gate dielectric transistors and their methods of fabrication Jan 11, 2018 Issued
Array ( [id] => 15123371 [patent_doc_number] => 20190348319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => PROCESS FOR SMOOTHING THE SURFACE OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/473475 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16473475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/473475
Process for smoothing the surface of a semiconductor-on-insulator substrate Jan 9, 2018 Issued
Array ( [id] => 12717082 [patent_doc_number] => 20180130860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => METHOD FOR FABRICATING COA ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/861002 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/861002
METHOD FOR FABRICATING COA ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE Jan 2, 2018 Abandoned
Array ( [id] => 18608175 [patent_doc_number] => 11749653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Multi-die, vertical-wire package-in-package apparatus, and methods of making same [patent_app_type] => utility [patent_app_number] => 16/647372 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16647372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/647372
Multi-die, vertical-wire package-in-package apparatus, and methods of making same Dec 27, 2017 Issued
Array ( [id] => 17607127 [patent_doc_number] => 11335619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/756450 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4878 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16756450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/756450
Semiconductor device Dec 26, 2017 Issued
Array ( [id] => 12669091 [patent_doc_number] => 20180114863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => FINFET TRANSISTOR GATE AND EPITAXY FORMATION [patent_app_type] => utility [patent_app_number] => 15/846445 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846445
FinFET transistor gate and epitaxy formation Dec 18, 2017 Issued
Array ( [id] => 16035355 [patent_doc_number] => 10680112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Gate all around vacuum channel transistor [patent_app_type] => utility [patent_app_number] => 15/820010 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 5177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820010
Gate all around vacuum channel transistor Nov 20, 2017 Issued
Array ( [id] => 16433077 [patent_doc_number] => 10833176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Selectively formed gate sidewall spacer [patent_app_type] => utility [patent_app_number] => 15/818828 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 4741 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818828
Selectively formed gate sidewall spacer Nov 20, 2017 Issued
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