Search

Yu-hsi David Sun

Examiner (ID: 17238)

Most Active Art Unit
2895
Art Unit(s)
2817, 2895, 4183
Total Applications
1196
Issued Applications
920
Pending Applications
80
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15514843 [patent_doc_number] => 10564002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => GPS features and functionality in an athletic watch system [patent_app_type] => utility [patent_app_number] => 15/609979 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 46 [patent_no_of_words] => 25322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609979
GPS features and functionality in an athletic watch system May 30, 2017 Issued
Array ( [id] => 11946152 [patent_doc_number] => 20170250303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'METHOD FOR MANUFACTURING POLYCRYSTALLINE SILICON THIN-FILM SOLAR CELLS BY MEANS METHOD FOR CRYSTALLIZING LARGE-AREA AMORPHOUS SILICON THIN FILM USING LINEAR ELECTRON BEAM' [patent_app_type] => utility [patent_app_number] => 15/592421 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10413 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592421
Method for manufacturing polycrystalline silicon thin-film solar cells by means method for crystallizing large-area amorphous silicon thin film using linear electron beam May 10, 2017 Issued
Array ( [id] => 14252613 [patent_doc_number] => 10276513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Integrated circuit with backside structures to reduce substrate warp [patent_app_type] => utility [patent_app_number] => 15/589195 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589195
Integrated circuit with backside structures to reduce substrate warp May 7, 2017 Issued
Array ( [id] => 11824972 [patent_doc_number] => 20170213909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Method for Fabricating a Shallow and Narrow Trench FET' [patent_app_type] => utility [patent_app_number] => 15/483544 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3991 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483544 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483544
Method for Fabricating a Shallow and Narrow Trench FET Apr 9, 2017 Abandoned
Array ( [id] => 11825036 [patent_doc_number] => 20170213973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'ORGANIC PHOTOELECTRIC DEVICE, AND IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/482017 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8566 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482017
Organic photoelectric device, and image sensor and electronic device including the same Apr 6, 2017 Issued
Array ( [id] => 13098981 [patent_doc_number] => 10068836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Metal gate transistor, integrated circuits, systems, and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 15/481802 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481802
Metal gate transistor, integrated circuits, systems, and fabrication methods thereof Apr 6, 2017 Issued
Array ( [id] => 11746708 [patent_doc_number] => 20170200781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY UTILIZING A CURVED SEMICONDUCTOR LAYER' [patent_app_type] => utility [patent_app_number] => 15/470213 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470213
Organic light emitting diode display utilizing a curved semiconductor layer Mar 26, 2017 Issued
Array ( [id] => 11732817 [patent_doc_number] => 20170194260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/465194 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11614 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465194
Stacked multilayer structure and manufacturing method thereof Mar 20, 2017 Issued
Array ( [id] => 15547879 [patent_doc_number] => 10573731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor transistor and method for forming the semiconductor transistor [patent_app_type] => utility [patent_app_number] => 15/458173 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 7371 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/458173
Semiconductor transistor and method for forming the semiconductor transistor Mar 13, 2017 Issued
Array ( [id] => 12223369 [patent_doc_number] => 20180061729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/457181 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/457181
Semiconductor package Mar 12, 2017 Issued
Array ( [id] => 13724079 [patent_doc_number] => 20170372995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/457260 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457260 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/457260
Fan-out semiconductor package Mar 12, 2017 Issued
Array ( [id] => 14573535 [patent_doc_number] => 20190214375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => Optoelectronic Semiconductor Component [patent_app_type] => utility [patent_app_number] => 16/071253 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16071253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/071253
Optoelectronic semiconductor component Mar 1, 2017 Issued
Array ( [id] => 11710473 [patent_doc_number] => 20170178972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/447126 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4839 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447126 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447126
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Mar 1, 2017 Abandoned
Array ( [id] => 14079257 [patent_doc_number] => 20190088516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => CHIP BONDING APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 16/080376 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16080376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/080376
Chip bonding apparatus and method Feb 26, 2017 Issued
Array ( [id] => 12162371 [patent_doc_number] => 20180033637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'METHODS FOR FABRICATING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/443370 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 6225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443370 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443370
Methods for fabricating semiconductor devices using a multilayer lithography process Feb 26, 2017 Issued
Array ( [id] => 14429881 [patent_doc_number] => 10319754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Method of fabricating crystalline island on substrate [patent_app_type] => utility [patent_app_number] => 15/429367 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 14311 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429367
Method of fabricating crystalline island on substrate Feb 9, 2017 Issued
Array ( [id] => 14644511 [patent_doc_number] => 10367006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Display Device [patent_app_type] => utility [patent_app_number] => 15/428340 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 42 [patent_no_of_words] => 22149 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428340 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428340
Display Device Feb 8, 2017 Issued
Array ( [id] => 11623396 [patent_doc_number] => 20170133585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD FOR FORMING A METAL CAP IN A SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/410501 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2370 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410501 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410501
METHOD FOR FORMING A METAL CAP IN A SEMICONDUCTOR MEMORY DEVICE Jan 18, 2017 Abandoned
Array ( [id] => 12872905 [patent_doc_number] => 20180182810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => INTEGRATED TWO-TERMINAL DEVICE WITH LOGIC DEVICE FOR EMBEDDED APPLICATION [patent_app_type] => utility [patent_app_number] => 15/393200 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393200
Integrated two-terminal device with logic device for embedded application Dec 27, 2016 Issued
Array ( [id] => 11544762 [patent_doc_number] => 20170098587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER' [patent_app_type] => utility [patent_app_number] => 15/387855 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387855
Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer Dec 21, 2016 Issued
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