
Yu-hsi David Sun
Examiner (ID: 2413, Phone: (571)270-5773 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 4183, 2895, 2817 |
| Total Applications | 1172 |
| Issued Applications | 906 |
| Pending Applications | 81 |
| Abandoned Applications | 211 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19886830
[patent_doc_number] => 12272557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 18/363563
[patent_app_country] => US
[patent_app_date] => 2023-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 37
[patent_no_of_words] => 12207
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363563
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363563 | Semiconductor device and method | Jul 31, 2023 | Issued |
Array
(
[id] => 19634583
[patent_doc_number] => 20240413032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => INSULATION LAYER FOR A SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/362128
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5396
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362128
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362128 | INSULATION LAYER FOR A SEMICONDUCTOR PACKAGE | Jul 30, 2023 | Pending |
Array
(
[id] => 19842696
[patent_doc_number] => 12255096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Semiconductor device with reduced contact resistance and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/361592
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 28
[patent_no_of_words] => 11190
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361592
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361592 | Semiconductor device with reduced contact resistance and methods of forming the same | Jul 27, 2023 | Issued |
Array
(
[id] => 19619314
[patent_doc_number] => 20240404994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => THERMALLY CONDUCTIVE SPACER
[patent_app_type] => utility
[patent_app_number] => 18/359645
[patent_app_country] => US
[patent_app_date] => 2023-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6080
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359645
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/359645 | THERMALLY CONDUCTIVE SPACER | Jul 25, 2023 | Pending |
Array
(
[id] => 18774460
[patent_doc_number] => 20230369291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => SEMICONDUCTOR ASSEMBLIES WITH SYSTEMS AND METHODS FOR MANAGING HIGH DIE STACK STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/225369
[patent_app_country] => US
[patent_app_date] => 2023-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7584
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225369
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/225369 | Semiconductor assemblies with systems and methods for managing high die stack structures | Jul 23, 2023 | Issued |
Array
(
[id] => 18774511
[patent_doc_number] => 20230369342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => Semiconductor Device
[patent_app_type] => utility
[patent_app_number] => 18/224224
[patent_app_country] => US
[patent_app_date] => 2023-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224224
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/224224 | Semiconductor device | Jul 19, 2023 | Issued |
Array
(
[id] => 19146394
[patent_doc_number] => 20240145424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => NAND DIE WITH WIRE-BOND INDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/355111
[patent_app_country] => US
[patent_app_date] => 2023-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355111
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/355111 | NAND DIE WITH WIRE-BOND INDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES | Jul 18, 2023 | Pending |
Array
(
[id] => 18757621
[patent_doc_number] => 20230361084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/353343
[patent_app_country] => US
[patent_app_date] => 2023-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4739
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353343
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/353343 | Semiconductor package and manufacturing method thereof | Jul 16, 2023 | Issued |
Array
(
[id] => 19733819
[patent_doc_number] => 12211821
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Package-on-package assembly with wire bond vias
[patent_app_type] => utility
[patent_app_number] => 18/221171
[patent_app_country] => US
[patent_app_date] => 2023-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 68
[patent_no_of_words] => 17454
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221171
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/221171 | Package-on-package assembly with wire bond vias | Jul 11, 2023 | Issued |
Array
(
[id] => 19484227
[patent_doc_number] => 20240332269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE, FABRICATION METHOD AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/220768
[patent_app_country] => US
[patent_app_date] => 2023-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7854
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220768
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/220768 | SEMICONDUCTOR PACKAGE STRUCTURE, FABRICATION METHOD AND MEMORY SYSTEM | Jul 10, 2023 | Pending |
Array
(
[id] => 18898619
[patent_doc_number] => 20240014104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => Semiconductor Package or a Printed Circuit Board, Both Modified to One or More of Reduce, Inverse or Utilize Magnetic Coupling Caused by the Load Current of a Semiconductor Transistor
[patent_app_type] => utility
[patent_app_number] => 18/217044
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7138
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217044
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/217044 | Semiconductor Package or a Printed Circuit Board, Both Modified to One or More of Reduce, Inverse or Utilize Magnetic Coupling Caused by the Load Current of a Semiconductor Transistor | Jun 29, 2023 | Pending |
Array
(
[id] => 18712895
[patent_doc_number] => 20230335528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => BONDING WIRE FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/211069
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16838
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/211069 | BONDING WIRE FOR SEMICONDUCTOR DEVICES | Jun 15, 2023 | Abandoned |
Array
(
[id] => 19720395
[patent_doc_number] => 12205940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Semiconductor package structure and packaging method thereof
[patent_app_type] => utility
[patent_app_number] => 18/210516
[patent_app_country] => US
[patent_app_date] => 2023-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9200
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210516
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/210516 | Semiconductor package structure and packaging method thereof | Jun 14, 2023 | Issued |
Array
(
[id] => 18698571
[patent_doc_number] => 20230329053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => FLEXIBLE DISPLAY
[patent_app_type] => utility
[patent_app_number] => 18/209556
[patent_app_country] => US
[patent_app_date] => 2023-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7085
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209556
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/209556 | Flexible display | Jun 13, 2023 | Issued |
Array
(
[id] => 18975303
[patent_doc_number] => 20240055395
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP BONDED TO MEMORY DIES USING WIRES
[patent_app_type] => utility
[patent_app_number] => 18/206201
[patent_app_country] => US
[patent_app_date] => 2023-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7364
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206201
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206201 | SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP BONDED TO MEMORY DIES USING WIRES | Jun 5, 2023 | Pending |
Array
(
[id] => 20113220
[patent_doc_number] => 12363975
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
[patent_app_type] => utility
[patent_app_number] => 18/200153
[patent_app_country] => US
[patent_app_date] => 2023-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 26
[patent_no_of_words] => 2125
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200153
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/200153 | Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells | May 21, 2023 | Issued |
Array
(
[id] => 19589903
[patent_doc_number] => 20240387460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/320553
[patent_app_country] => US
[patent_app_date] => 2023-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7371
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320553
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/320553 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | May 18, 2023 | Pending |
Array
(
[id] => 18848901
[patent_doc_number] => 20230411305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => METHOD FOR SELECTIVELY FORMING A SHIELDING LAYER ON A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/315479
[patent_app_country] => US
[patent_app_date] => 2023-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4434
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315479
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/315479 | METHOD FOR SELECTIVELY FORMING A SHIELDING LAYER ON A SEMICONDUCTOR DEVICE | May 9, 2023 | Pending |
Array
(
[id] => 18774531
[patent_doc_number] => 20230369362
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/312552
[patent_app_country] => US
[patent_app_date] => 2023-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4679
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312552
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/312552 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF | May 3, 2023 | Pending |
Array
(
[id] => 20148457
[patent_doc_number] => 12382819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-05
[patent_title] => Organic light emitting diode display device
[patent_app_type] => utility
[patent_app_number] => 18/301345
[patent_app_country] => US
[patent_app_date] => 2023-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301345
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/301345 | Organic light emitting diode display device | Apr 16, 2023 | Issued |