Search

Yu-hsi David Sun

Examiner (ID: 2413, Phone: (571)270-5773 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
4183, 2895, 2817
Total Applications
1172
Issued Applications
906
Pending Applications
81
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19926372 [patent_doc_number] => 12300668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/889053 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889053
Semiconductor package Aug 15, 2022 Issued
Array ( [id] => 18243088 [patent_doc_number] => 20230075399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => INTEGRATED CIRCUIT (IC) AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/888739 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888739
Integrated circuit (IC) and electronic apparatus Aug 15, 2022 Issued
Array ( [id] => 20229300 [patent_doc_number] => 12417956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Double-side cooling-type semiconductor device [patent_app_type] => utility [patent_app_number] => 17/889097 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889097
Double-side cooling-type semiconductor device Aug 15, 2022 Issued
Array ( [id] => 18975239 [patent_doc_number] => 20240055331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SMALL OUTLINE TRANSISTOR WITH THERMAL FLAT LEAD [patent_app_type] => utility [patent_app_number] => 17/887790 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887790
SMALL OUTLINE TRANSISTOR WITH THERMAL FLAT LEAD Aug 14, 2022 Pending
Array ( [id] => 20175998 [patent_doc_number] => 12394755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Inter-die signal load reduction technique in multi-die package [patent_app_type] => utility [patent_app_number] => 17/887362 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3489 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887362
Inter-die signal load reduction technique in multi-die package Aug 11, 2022 Issued
Array ( [id] => 18227657 [patent_doc_number] => 20230066651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHOD OF MANUFACTURING CHIPS [patent_app_type] => utility [patent_app_number] => 17/819018 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819018
Method of manufacturing chips Aug 10, 2022 Issued
Array ( [id] => 18743412 [patent_doc_number] => 20230352400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING VIA STRUCTURES HAVING A NARROW UPPER PORTION, AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/880554 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880554
INTEGRATED CIRCUIT DEVICES INCLUDING VIA STRUCTURES HAVING A NARROW UPPER PORTION, AND RELATED FABRICATION METHODS Aug 2, 2022 Pending
Array ( [id] => 18008563 [patent_doc_number] => 20220367330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ELECTRONICS UNIT WITH INTEGRATED METALLIC PATTERN [patent_app_type] => utility [patent_app_number] => 17/878436 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878436
Electronics unit with integrated metallic pattern Jul 31, 2022 Issued
Array ( [id] => 19399755 [patent_doc_number] => 12074143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 17/874598 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874598
Integrated circuit package and method Jul 26, 2022 Issued
Array ( [id] => 18223324 [patent_doc_number] => 20230062318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/872543 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872543
Semiconductor device Jul 24, 2022 Issued
Array ( [id] => 19314410 [patent_doc_number] => 12040235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/870343 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870343
Semiconductor device and method of manufacture Jul 20, 2022 Issued
Array ( [id] => 17986299 [patent_doc_number] => 20220352336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Transistor Gates and Method of Forming [patent_app_type] => utility [patent_app_number] => 17/869430 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869430
Transistor gates and method of forming Jul 19, 2022 Issued
Array ( [id] => 18680061 [patent_doc_number] => 20230317719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => THREE-DIMENSIONAL BIPOLAR-CMOS-DMOS (BCD) STRUCTURE WITH INTEGRATED BACK-SIDE CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/865967 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865967
Three-dimensional bipolar-CMOS-DMOS (BCD) structure with integrated back-side capacitor Jul 14, 2022 Issued
Array ( [id] => 18680061 [patent_doc_number] => 20230317719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => THREE-DIMENSIONAL BIPOLAR-CMOS-DMOS (BCD) STRUCTURE WITH INTEGRATED BACK-SIDE CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/865967 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865967
Three-dimensional bipolar-CMOS-DMOS (BCD) structure with integrated back-side capacitor Jul 14, 2022 Issued
Array ( [id] => 17993539 [patent_doc_number] => 20220359576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/865300 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865300
Light emitting display device Jul 13, 2022 Issued
Array ( [id] => 18898683 [patent_doc_number] => 20240014168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH FIXING FEATURE ON WHICH BONDING WIRE IS DISPOSED [patent_app_type] => utility [patent_app_number] => 17/860392 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860392
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH FIXING FEATURE ON WHICH BONDING WIRE IS DISPOSED Jul 7, 2022 Pending
Array ( [id] => 20375325 [patent_doc_number] => 12482769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Selective plating for packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/855695 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 3319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855695
Selective plating for packaged semiconductor devices Jun 29, 2022 Issued
Array ( [id] => 17933241 [patent_doc_number] => 20220328367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => METHODS OF DETECTING BONDING BETWEEN A BONDING WIRE AND A BONDING LOCATION ON A WIRE BONDING MACHINE [patent_app_type] => utility [patent_app_number] => 17/852561 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852561
Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine Jun 28, 2022 Issued
Array ( [id] => 19566743 [patent_doc_number] => 12141515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Memory cell layout for low current field-induced MRAM [patent_app_type] => utility [patent_app_number] => 17/842928 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1664 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842928
Memory cell layout for low current field-induced MRAM Jun 16, 2022 Issued
Array ( [id] => 18112922 [patent_doc_number] => 20230005802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/843799 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843799
Build-up package for integrated circuit devices, and methods of making same Jun 16, 2022 Issued
Menu