Yuhui R. Pan

Array ( [id] => 17031075 [patent_doc_number] => 11092885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Manufacturing methods of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/845459 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18546412 [patent_doc_number] => 11719760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Probabilistic determination of transformer end of life [patent_app_type] => utility [patent_app_number] => 16/843684 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 9415 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16535550 [patent_doc_number] => 10878151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Glitch occurring point detection apparatus and method [patent_app_type] => utility [patent_app_number] => 16/843720 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3673 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16864894 [patent_doc_number] => 11023638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Method for reducing cost and increasing accuracy of variational quantum circuit optimization [patent_app_type] => utility [patent_app_number] => 16/840935 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16363494 [patent_doc_number] => 20200320245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Test Generation Systems And Methods [patent_app_type] => utility [patent_app_number] => 16/841346 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17751169 [patent_doc_number] => 20220229374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD OF DETERMINING CHARACTERISTIC OF PATTERNING PROCESS BASED ON DEFECT FOR REDUCING HOTSPOT [patent_app_type] => utility [patent_app_number] => 17/605358 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17605358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16834263 [patent_doc_number] => 11010518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Mapping logical qubits on a quantum circuit [patent_app_type] => utility [patent_app_number] => 16/819994 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14330 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16273818 [patent_doc_number] => 20200275306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => MODULAR TRAFFIC CONTROL FUNCTIONS IN A TELECOMMUNICATION NETWORK [patent_app_type] => utility [patent_app_number] => 16/802459 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16660728 [patent_doc_number] => 20210057365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => METHOD AND SYSTEM FOR VERIFYING INTEGRATED CIRCUIT STACK HAVING PHOTONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/801160 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16018591 [patent_doc_number] => 20200184139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SYSTEM FOR AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/793693 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18235140 [patent_doc_number] => 11599699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => System and method for autonomous printed circuit board design using machine learning techniques [patent_app_type] => utility [patent_app_number] => 16/785972 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16994051 [patent_doc_number] => 20210232471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => EMULATION LATCH TO CAPTURE STATE [patent_app_type] => utility [patent_app_number] => 16/773002 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16552083 [patent_doc_number] => 10885244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout [patent_app_type] => utility [patent_app_number] => 16/739624 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 16357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15869185 [patent_doc_number] => 20200141996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY [patent_app_type] => utility [patent_app_number] => 16/733573 [patent_app_country] => US [patent_app_date] => 2020-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19539410 [patent_doc_number] => 12131967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Electronic device package with board level reliability [patent_app_type] => utility [patent_app_number] => 16/725738 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 8145 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15773661 [patent_doc_number] => 20200117848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME [patent_app_type] => utility [patent_app_number] => 16/711112 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17471422 [patent_doc_number] => 11277918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Current redistribution in a printed circuit board [patent_app_type] => utility [patent_app_number] => 16/700198 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17478094 [patent_doc_number] => 20220085598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => BATTERY PROTECTION CIRCUIT, BATTERY PROTECTION BOARD, BATTERY, AND TERMINAL DEVICE [patent_app_type] => utility [patent_app_number] => 17/416519 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17416519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16307766 [patent_doc_number] => 10776560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Mapping intermediate material properties to target properties to screen materials [patent_app_type] => utility [patent_app_number] => 16/691306 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8629 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18119588 [patent_doc_number] => 11550983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method for determining an electrical model of a string of photovoltaic modules, diagnostic method and device associated therewith [patent_app_type] => utility [patent_app_number] => 16/682807 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11927 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682807 [rel_patent_id] =>[rel_patent_doc_number] =>)