Search

Yuhui R. Pan

Examiner (ID: 4536, Phone: (571)272-9872 , Office: P/2121 )

Most Active Art Unit
2116
Art Unit(s)
2116, 2121, 2127
Total Applications
645
Issued Applications
498
Pending Applications
67
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16605432 [patent_doc_number] => 10906421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Wireless automatic charging system for electric vehicles [patent_app_type] => utility [patent_app_number] => 16/228788 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2110 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228788
Wireless automatic charging system for electric vehicles Dec 20, 2018 Issued
Array ( [id] => 17772931 [patent_doc_number] => 11404889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Power saving circuit for embedded battery applications [patent_app_type] => utility [patent_app_number] => 16/229846 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229846
Power saving circuit for embedded battery applications Dec 20, 2018 Issued
Array ( [id] => 16903548 [patent_doc_number] => 20210182464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => FPGA SYSTEM, PARTIAL RECONFIGURATION EXECUTION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/771503 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16771503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/771503
FPGA system, partial reconfiguration execution method, and storage medium Dec 4, 2018 Issued
Array ( [id] => 18262338 [patent_doc_number] => 11610040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-21 [patent_title] => System interconnect architecture using dynamic bitwise switch and low-latency input/output [patent_app_type] => utility [patent_app_number] => 16/209597 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209597
System interconnect architecture using dynamic bitwise switch and low-latency input/output Dec 3, 2018 Issued
Array ( [id] => 17062241 [patent_doc_number] => 11106846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Systems and methods for emulation data array compaction [patent_app_type] => utility [patent_app_number] => 16/208431 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208431
Systems and methods for emulation data array compaction Dec 2, 2018 Issued
Array ( [id] => 15998515 [patent_doc_number] => 20200175128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => HARDWARE INCREMENTAL MODEL CHECKING VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/203716 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203716
Hardware incremental model checking verification Nov 28, 2018 Issued
Array ( [id] => 15758363 [patent_doc_number] => 10621297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Initial-state and next-state value folding [patent_app_type] => utility [patent_app_number] => 16/145385 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145385
Initial-state and next-state value folding Sep 27, 2018 Issued
Array ( [id] => 16355532 [patent_doc_number] => 10796044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Interface connectivity for printed circuit board schematic [patent_app_type] => utility [patent_app_number] => 16/146749 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146749
Interface connectivity for printed circuit board schematic Sep 27, 2018 Issued
Array ( [id] => 16292476 [patent_doc_number] => 10769328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Generating a template-driven schematic from a netlist of electronic circuits [patent_app_type] => utility [patent_app_number] => 16/146008 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146008 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146008
Generating a template-driven schematic from a netlist of electronic circuits Sep 27, 2018 Issued
Array ( [id] => 14669923 [patent_doc_number] => 10372863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Tool for modular circuit board design [patent_app_type] => utility [patent_app_number] => 16/106584 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8693 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106584
Tool for modular circuit board design Aug 20, 2018 Issued
Array ( [id] => 15399613 [patent_doc_number] => 10540464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-21 [patent_title] => Critical path aware voltage drop analysis of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/103888 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103888
Critical path aware voltage drop analysis of an integrated circuit Aug 13, 2018 Issued
Array ( [id] => 14585919 [patent_doc_number] => 20190220568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/102888 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102888
Semiconductor device Aug 13, 2018 Issued
Array ( [id] => 15531061 [patent_doc_number] => 20200057836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONSTRAINTS [patent_app_type] => utility [patent_app_number] => 16/103011 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103011
Autonomous placement to satisfy self-aligned double patterning constraints Aug 13, 2018 Issued
Array ( [id] => 16337805 [patent_doc_number] => 10788759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Prediction based chucking and lithography control optimization [patent_app_type] => utility [patent_app_number] => 16/049266 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3591 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049266
Prediction based chucking and lithography control optimization Jul 29, 2018 Issued
Array ( [id] => 13627597 [patent_doc_number] => 20180365350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => GENERATING CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/001122 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001122
GENERATING CIRCUITS Jun 5, 2018 Abandoned
Array ( [id] => 13411901 [patent_doc_number] => 20180257493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => ELECTRIC POWER RECEPTION DEVICE FOR VEHICLE, ELECTRIC POWER TRANSMISSION DEVICE, AND NON-CONTACT ELECTRIC POWER TRANSMISSION/RECEPTION SYSTEM [patent_app_type] => utility [patent_app_number] => 15/981293 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981293
ELECTRIC POWER RECEPTION DEVICE FOR VEHICLE, ELECTRIC POWER TRANSMISSION DEVICE, AND NON-CONTACT ELECTRIC POWER TRANSMISSION/RECEPTION SYSTEM May 15, 2018 Abandoned
Array ( [id] => 15168091 [patent_doc_number] => 10489542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Machine learning based post route path delay estimator from synthesis netlist [patent_app_type] => utility [patent_app_number] => 15/960833 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5892 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960833
Machine learning based post route path delay estimator from synthesis netlist Apr 23, 2018 Issued
Array ( [id] => 15577175 [patent_doc_number] => 10578963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Mask pattern generation based on fast marching method [patent_app_type] => utility [patent_app_number] => 15/959968 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 12379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959968
Mask pattern generation based on fast marching method Apr 22, 2018 Issued
Array ( [id] => 15028195 [patent_doc_number] => 20190325102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => CIRCUIT GENERATION BASED ON ZERO WIRE LOAD ASSERTIONS [patent_app_type] => utility [patent_app_number] => 15/957959 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957959 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957959
Circuit generation based on zero wire load assertions Apr 19, 2018 Issued
Array ( [id] => 13317991 [patent_doc_number] => 20180210533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => VOLTAGE AND FREQUENCY BALANCING AT NOMINAL POINT [patent_app_type] => utility [patent_app_number] => 15/952558 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952558
Voltage and frequency balancing at nominal point Apr 12, 2018 Issued
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