Search

Yuhui R. Pan

Examiner (ID: 4536, Phone: (571)272-9872 , Office: P/2121 )

Most Active Art Unit
2116
Art Unit(s)
2116, 2121, 2127
Total Applications
645
Issued Applications
498
Pending Applications
67
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7793147 [patent_doc_number] => 20120054703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Virtual Flat Traversal Of A Hierarchical Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/868717 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054703.pdf [firstpage_image] =>[orig_patent_app_number] => 12868717 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868717
Virtual Flat Traversal Of A Hierarchical Circuit Design Aug 24, 2010 Abandoned
Array ( [id] => 6074264 [patent_doc_number] => 20110047520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Partition Response Surface Modeling' [patent_app_type] => utility [patent_app_number] => 12/861777 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6951 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047520.pdf [firstpage_image] =>[orig_patent_app_number] => 12861777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/861777
Partition response surface modeling Aug 22, 2010 Issued
Array ( [id] => 8391243 [patent_doc_number] => 20120229083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'HANDHELD TOOL BATTERY CHARGING MEANS' [patent_app_type] => utility [patent_app_number] => 13/395719 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3452 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13395719 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/395719
HANDHELD TOOL BATTERY CHARGING MEANS Jul 27, 2010 Abandoned
Array ( [id] => 8763388 [patent_doc_number] => 08423927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Simulation of the image projected by a mask' [patent_app_type] => utility [patent_app_number] => 12/839817 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4994 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12839817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/839817
Simulation of the image projected by a mask Jul 19, 2010 Issued
Array ( [id] => 8678834 [patent_doc_number] => 08386971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and apparatus for low delay recursive filter design' [patent_app_type] => utility [patent_app_number] => 12/838897 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2105 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12838897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838897
Method and apparatus for low delay recursive filter design Jul 18, 2010 Issued
Array ( [id] => 7736009 [patent_doc_number] => 20120017188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'METHOD OF DETERMINING EVENT BASED ENERGY WEIGHTS FOR DIGITAL POWER ESTIMATION' [patent_app_type] => utility [patent_app_number] => 12/838767 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4222 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20120017188.pdf [firstpage_image] =>[orig_patent_app_number] => 12838767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838767
Method of determining event based energy weights for digital power estimation Jul 18, 2010 Issued
Array ( [id] => 8461018 [patent_doc_number] => 08296704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and apparatus for simultaneous switching noise optimization' [patent_app_type] => utility [patent_app_number] => 12/833797 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12833797 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/833797
Method and apparatus for simultaneous switching noise optimization Jul 8, 2010 Issued
Array ( [id] => 8540604 [patent_doc_number] => 08316332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-20 [patent_title] => 'Constraint minimization method for formal verification' [patent_app_type] => utility [patent_app_number] => 12/831497 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7179 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12831497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831497
Constraint minimization method for formal verification Jul 6, 2010 Issued
Array ( [id] => 8060387 [patent_doc_number] => 20110246829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Method for Fast Detection of Node Mergers and Simplification of a Circuit' [patent_app_type] => utility [patent_app_number] => 12/830457 [patent_app_country] => US [patent_app_date] => 2010-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5268 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246829.pdf [firstpage_image] =>[orig_patent_app_number] => 12830457 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/830457
Method for Fast Detection of Node Mergers and Simplification of a Circuit Jul 5, 2010 Abandoned
Array ( [id] => 6100655 [patent_doc_number] => 20110004860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'DESIGN METHOD AND TOOL FOR DESIGNING ELECTRONIC CIRCUITS ON A PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/829096 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004860.pdf [firstpage_image] =>[orig_patent_app_number] => 12829096 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829096
Method and tool for designing electronic circuits on a printed circuit board Jun 30, 2010 Issued
Array ( [id] => 8214297 [patent_doc_number] => 20120131529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEFECT CLASSIFYING METHOD, SEMICONDUCTOR DEFECT CLASSIFYING APPARATUS, AND SEMICONDUCTOR DEFECT CLASSIFYING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/382437 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6861 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131529.pdf [firstpage_image] =>[orig_patent_app_number] => 13382437 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/382437
Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program May 13, 2010 Issued
Array ( [id] => 6535424 [patent_doc_number] => 20100218160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING A PROCESS MODEL THAT MODELS THE IMPACT OF A CAR/PEB ON THE RESIST PROFILE' [patent_app_type] => utility [patent_app_number] => 12/774522 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4742 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218160.pdf [firstpage_image] =>[orig_patent_app_number] => 12774522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774522
Method and apparatus for determining a process model that models the impact of a CAR/PEB on the resist profile May 4, 2010 Issued
Array ( [id] => 7575586 [patent_doc_number] => 20110271242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays' [patent_app_type] => utility [patent_app_number] => 12/771677 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271242.pdf [firstpage_image] =>[orig_patent_app_number] => 12771677 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771677
Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. Apr 29, 2010 Issued
Array ( [id] => 9116327 [patent_doc_number] => 08572519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Method and apparatus for reducing implant topography reflection effect' [patent_app_type] => utility [patent_app_number] => 12/758147 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758147
Method and apparatus for reducing implant topography reflection effect Apr 11, 2010 Issued
Array ( [id] => 8849436 [patent_doc_number] => 08458636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'Filling vacant areas of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/727227 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12727227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/727227
Filling vacant areas of an integrated circuit design Mar 17, 2010 Issued
Array ( [id] => 8837307 [patent_doc_number] => 08453076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Wavefront engineering of mask data for semiconductor device design' [patent_app_type] => utility [patent_app_number] => 12/725287 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12725287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725287
Wavefront engineering of mask data for semiconductor device design Mar 15, 2010 Issued
Array ( [id] => 8412691 [patent_doc_number] => 08276102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Spatial correlation-based estimation of yield of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/718567 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 10508 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718567
Spatial correlation-based estimation of yield of integrated circuits Mar 4, 2010 Issued
Array ( [id] => 6652455 [patent_doc_number] => 20100229144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'SYSTEM AND METHOD FOR BEHAVIORAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/717377 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5505 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229144.pdf [firstpage_image] =>[orig_patent_app_number] => 12717377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717377
SYSTEM AND METHOD FOR BEHAVIORAL SYNTHESIS Mar 3, 2010 Abandoned
Array ( [id] => 8461013 [patent_doc_number] => 08296699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification' [patent_app_type] => utility [patent_app_number] => 12/714027 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7576 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12714027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714027
Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification Feb 25, 2010 Issued
Array ( [id] => 7728942 [patent_doc_number] => 20120013373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'SEMICONDUCTOR DEVICE, CIRCUIT CORRECTION METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/203197 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20120013373.pdf [firstpage_image] =>[orig_patent_app_number] => 13203197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/203197
SEMICONDUCTOR DEVICE, CIRCUIT CORRECTION METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM Feb 8, 2010 Abandoned
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