Yuzhen Ge

Array ( [id] => 2739389 [patent_doc_number] => 04998072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'High resolution direct digital synthesizer' [patent_app_type] => 1 [patent_app_number] => 7/482290 [patent_app_country] => US [patent_app_date] => 1990-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3937 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/998/04998072.pdf [firstpage_image] =>[orig_patent_app_number] => 482290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2583004 [patent_doc_number] => 04973863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'TTL-ECL interface circuit' [patent_app_type] => 1 [patent_app_number] => 7/458209 [patent_app_country] => US [patent_app_date] => 1989-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/973/04973863.pdf [firstpage_image] =>[orig_patent_app_number] => 458209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2699660 [patent_doc_number] => 04990799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Low-hysteresis regenerative comparator' [patent_app_type] => 1 [patent_app_number] => 7/457121 [patent_app_country] => US [patent_app_date] => 1989-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4479 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/990/04990799.pdf [firstpage_image] =>[orig_patent_app_number] => 457121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2710338 [patent_doc_number] => 04992681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Logic level converting circuit' [patent_app_type] => 1 [patent_app_number] => 7/451316 [patent_app_country] => US [patent_app_date] => 1989-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3710 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992681.pdf [firstpage_image] =>[orig_patent_app_number] => 451316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2727848 [patent_doc_number] => 05025224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Incremental integrator circuit' [patent_app_type] => 1 [patent_app_number] => 7/447749 [patent_app_country] => US [patent_app_date] => 1989-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2927 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/025/05025224.pdf [firstpage_image] =>[orig_patent_app_number] => 447749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2650204 [patent_doc_number] => 04980585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Method and apparatus for synthesizing digital waveforms' [patent_app_type] => 1 [patent_app_number] => 7/444670 [patent_app_country] => US [patent_app_date] => 1989-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4313 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980585.pdf [firstpage_image] =>[orig_patent_app_number] => 444670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2711508 [patent_doc_number] => 04992743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Dual-tone direct digital synthesizer' [patent_app_type] => 1 [patent_app_number] => 7/436634 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4873 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992743.pdf [firstpage_image] =>[orig_patent_app_number] => 436634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2600222 [patent_doc_number] => 04975605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-04 [patent_title] => 'Synchronous delay line with automatic reset' [patent_app_type] => 1 [patent_app_number] => 7/434340 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7952 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/975/04975605.pdf [firstpage_image] =>[orig_patent_app_number] => 434340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2767410 [patent_doc_number] => 04994695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Synchronous delay line with quadrature clock phases' [patent_app_type] => 1 [patent_app_number] => 7/434408 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6191 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994695.pdf [firstpage_image] =>[orig_patent_app_number] => 434408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2593363 [patent_doc_number] => 04970408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-13 [patent_title] => 'CMOS power-on reset circuit' [patent_app_type] => 1 [patent_app_number] => 7/428678 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1680 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/970/04970408.pdf [firstpage_image] =>[orig_patent_app_number] => 428678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2713022 [patent_doc_number] => 04982165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Set-on oscillator' [patent_app_type] => 1 [patent_app_number] => 7/424418 [patent_app_country] => US [patent_app_date] => 1989-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3637 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/982/04982165.pdf [firstpage_image] =>[orig_patent_app_number] => 424418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2712415 [patent_doc_number] => 05014013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Antilog circuit with automatic gain control' [patent_app_type] => 1 [patent_app_number] => 7/418295 [patent_app_country] => US [patent_app_date] => 1989-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014013.pdf [firstpage_image] =>[orig_patent_app_number] => 418295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2749592 [patent_doc_number] => 05012132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Dual mode high voltage coupler' [patent_app_type] => 1 [patent_app_number] => 7/417594 [patent_app_country] => US [patent_app_date] => 1989-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012132.pdf [firstpage_image] =>[orig_patent_app_number] => 417594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2749220 [patent_doc_number] => 05003198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'Circuit technique for biasing complementary Darlington emitter follower stages' [patent_app_type] => 1 [patent_app_number] => 7/414048 [patent_app_country] => US [patent_app_date] => 1989-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1780 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003198.pdf [firstpage_image] =>[orig_patent_app_number] => 414048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2710377 [patent_doc_number] => 04992683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Load driver with reduced dissipation under reverse-battery conditions' [patent_app_type] => 1 [patent_app_number] => 7/413933 [patent_app_country] => US [patent_app_date] => 1989-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1665 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992683.pdf [firstpage_image] =>[orig_patent_app_number] => 413933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2699067 [patent_doc_number] => 04996446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Semiconductor device having a reverse bias voltage generator' [patent_app_type] => 1 [patent_app_number] => 7/413336 [patent_app_country] => US [patent_app_date] => 1989-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3570 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996446.pdf [firstpage_image] =>[orig_patent_app_number] => 413336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2699029 [patent_doc_number] => 04996444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Clock recovery circuit' [patent_app_type] => 1 [patent_app_number] => 7/410376 [patent_app_country] => US [patent_app_date] => 1989-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2739 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996444.pdf [firstpage_image] =>[orig_patent_app_number] => 410376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2710674 [patent_doc_number] => 05001363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-19 [patent_title] => 'Circuit for measuring rotary shaft off-sets' [patent_app_type] => 1 [patent_app_number] => 7/409784 [patent_app_country] => US [patent_app_date] => 1989-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2290 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/001/05001363.pdf [firstpage_image] =>[orig_patent_app_number] => 409784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2750977 [patent_doc_number] => 05015891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Output feedback control circuit for integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/407756 [patent_app_country] => US [patent_app_date] => 1989-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3899 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/015/05015891.pdf [firstpage_image] =>[orig_patent_app_number] => 407756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2673125 [patent_doc_number] => 04999526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Apparatus for synchronizing clock signals' [patent_app_type] => 1 [patent_app_number] => 7/384384 [patent_app_country] => US [patent_app_date] => 1989-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2376 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999526.pdf [firstpage_image] =>[orig_patent_app_number] => 384384 [rel_patent_id] =>[rel_patent_doc_number] =>)