Search

Yvonne Michele Horton

Examiner (ID: 7193)

Most Active Art Unit
3635
Art Unit(s)
3635, 3504, 3621
Total Applications
1111
Issued Applications
876
Pending Applications
59
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7021577 [patent_doc_number] => 20050223202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Branch prediction in a pipelined processor' [patent_app_type] => utility [patent_app_number] => 10/813268 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3429 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223202.pdf [firstpage_image] =>[orig_patent_app_number] => 10813268 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813268
Branch prediction in a pipelined processor Mar 30, 2004 Abandoned
Array ( [id] => 7333240 [patent_doc_number] => 20040255102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Data processing apparatus and method for transferring data values between a register file and a memory' [patent_app_type] => new [patent_app_number] => 10/812034 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8089 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255102.pdf [firstpage_image] =>[orig_patent_app_number] => 10812034 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812034
Data processing apparatus and method for transferring data values between a register file and a memory Mar 29, 2004 Abandoned
Array ( [id] => 6999647 [patent_doc_number] => 20050138323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Accumulator shadow register systems and methods' [patent_app_type] => utility [patent_app_number] => 10/739419 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2649 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138323.pdf [firstpage_image] =>[orig_patent_app_number] => 10739419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739419
Accumulator shadow register systems and methods Dec 17, 2003 Abandoned
Array ( [id] => 568548 [patent_doc_number] => 07171544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Run-time parallelization of loops in computer programs by access patterns' [patent_app_type] => utility [patent_app_number] => 10/736343 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9572 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/171/07171544.pdf [firstpage_image] =>[orig_patent_app_number] => 10736343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736343
Run-time parallelization of loops in computer programs by access patterns Dec 14, 2003 Issued
Array ( [id] => 7100319 [patent_doc_number] => 20050132163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning' [patent_app_type] => utility [patent_app_number] => 10/734340 [patent_app_country] => US [patent_app_date] => 2003-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 10007 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132163.pdf [firstpage_image] =>[orig_patent_app_number] => 10734340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734340
Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning Dec 12, 2003 Issued
Array ( [id] => 7118861 [patent_doc_number] => 20050071608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method and apparatus for selectively counting instructions and data accesses' [patent_app_type] => utility [patent_app_number] => 10/674604 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15236 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071608.pdf [firstpage_image] =>[orig_patent_app_number] => 10674604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674604
Method and apparatus for selectively counting instructions and data accesses Sep 29, 2003 Abandoned
Array ( [id] => 653594 [patent_doc_number] => 07114055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word' [patent_app_type] => utility [patent_app_number] => 10/675759 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 10817 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114055.pdf [firstpage_image] =>[orig_patent_app_number] => 10675759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675759
Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word Sep 28, 2003 Issued
Array ( [id] => 671563 [patent_doc_number] => 07096345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof' [patent_app_type] => utility [patent_app_number] => 10/672774 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11152 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096345.pdf [firstpage_image] =>[orig_patent_app_number] => 10672774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672774
Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof Sep 25, 2003 Issued
Array ( [id] => 685455 [patent_doc_number] => 07082517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Superscalar microprocessor having multi-pipe dispatch and execution unit' [patent_app_type] => utility [patent_app_number] => 10/435806 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2878 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082517.pdf [firstpage_image] =>[orig_patent_app_number] => 10435806 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435806
Superscalar microprocessor having multi-pipe dispatch and execution unit May 11, 2003 Issued
Array ( [id] => 7436488 [patent_doc_number] => 20040230780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Dynamically adaptive associativity of a branch target buffer (BTB)' [patent_app_type] => new [patent_app_number] => 10/436397 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4330 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230780.pdf [firstpage_image] =>[orig_patent_app_number] => 10436397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436397
Dynamically adaptive associativity of a branch target buffer (BTB) May 11, 2003 Issued
Array ( [id] => 684748 [patent_doc_number] => 07085917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Multi-pipe dispatch and execution of complex instructions in a superscalar processor' [patent_app_type] => utility [patent_app_number] => 10/435983 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085917.pdf [firstpage_image] =>[orig_patent_app_number] => 10435983 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435983
Multi-pipe dispatch and execution of complex instructions in a superscalar processor May 11, 2003 Issued
Array ( [id] => 7434901 [patent_doc_number] => 20040230626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Computer system method for a one cycle implementation of test under mask instructions' [patent_app_type] => new [patent_app_number] => 10/436211 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3615 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230626.pdf [firstpage_image] =>[orig_patent_app_number] => 10436211 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436211
Computer system method for a one cycle implementation of test under mask instructions May 11, 2003 Abandoned
Array ( [id] => 7436448 [patent_doc_number] => 20040230775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Computer instructions for optimum performance of C-language string functions' [patent_app_type] => new [patent_app_number] => 10/435987 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3181 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230775.pdf [firstpage_image] =>[orig_patent_app_number] => 10435987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435987
Computer instructions for optimum performance of C-language string functions May 11, 2003 Abandoned
Array ( [id] => 7672125 [patent_doc_number] => 20040181654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'LOW POWER BRANCH PREDICTION TARGET BUFFER' [patent_app_type] => new [patent_app_number] => 10/249040 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181654.pdf [firstpage_image] =>[orig_patent_app_number] => 10249040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249040
LOW POWER BRANCH PREDICTION TARGET BUFFER Mar 10, 2003 Abandoned
Array ( [id] => 626408 [patent_doc_number] => 07139902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Implementation of an efficient instruction fetch pipeline utilizing a trace cache' [patent_app_type] => utility [patent_app_number] => 10/356984 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139902.pdf [firstpage_image] =>[orig_patent_app_number] => 10356984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356984
Implementation of an efficient instruction fetch pipeline utilizing a trace cache Feb 2, 2003 Issued
Array ( [id] => 7282302 [patent_doc_number] => 20040064679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Hierarchical scheduling windows' [patent_app_type] => new [patent_app_number] => 10/354360 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2565 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064679.pdf [firstpage_image] =>[orig_patent_app_number] => 10354360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/354360
Hierarchical scheduling windows Jan 28, 2003 Abandoned
Array ( [id] => 7673637 [patent_doc_number] => 20040128481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Efficient lossy instruction scheduling' [patent_app_type] => new [patent_app_number] => 10/334528 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5572 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128481.pdf [firstpage_image] =>[orig_patent_app_number] => 10334528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334528
Efficient instruction scheduling with lossy tracking of scheduling information Dec 30, 2002 Issued
Array ( [id] => 7673639 [patent_doc_number] => 20040128479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Method and apparatus for variable length instruction parallel decoding' [patent_app_type] => new [patent_app_number] => 10/331335 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8363 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128479.pdf [firstpage_image] =>[orig_patent_app_number] => 10331335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331335
Method and apparatus for variable length instruction parallel decoding Dec 30, 2002 Abandoned
Array ( [id] => 7673643 [patent_doc_number] => 20040128475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Widely accessible processor register file and method for use' [patent_app_type] => new [patent_app_number] => 10/331608 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4608 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128475.pdf [firstpage_image] =>[orig_patent_app_number] => 10331608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331608
Widely accessible processor register file and method for use Dec 30, 2002 Abandoned
Array ( [id] => 7601945 [patent_doc_number] => 07237099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor' [patent_app_type] => utility [patent_app_number] => 10/329986 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5794 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237099.pdf [firstpage_image] =>[orig_patent_app_number] => 10329986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329986
Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor Dec 26, 2002 Issued
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