Search

Yvonne Michele Horton

Examiner (ID: 7193)

Most Active Art Unit
3635
Art Unit(s)
3635, 3504, 3621
Total Applications
1111
Issued Applications
876
Pending Applications
59
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7174294 [patent_doc_number] => 20040078551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Method for operating a data processing device as well as contruction of a data processing device as a memory-programmable control unit' [patent_app_type] => new [patent_app_number] => 10/326261 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2774 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078551.pdf [firstpage_image] =>[orig_patent_app_number] => 10326261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326261
Method for operating a data processing device as well as contruction of a data processing device as a memory-programmable control unit Dec 22, 2002 Abandoned
Array ( [id] => 7476932 [patent_doc_number] => 20040123081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Mechanism to increase performance of control speculation' [patent_app_type] => new [patent_app_number] => 10/327556 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123081.pdf [firstpage_image] =>[orig_patent_app_number] => 10327556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327556
Mechanism to increase performance of control speculation Dec 19, 2002 Abandoned
Array ( [id] => 7476923 [patent_doc_number] => 20040123075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Extended loop prediction techniques' [patent_app_type] => new [patent_app_number] => 10/324951 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4072 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123075.pdf [firstpage_image] =>[orig_patent_app_number] => 10324951 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324951
Extended loop prediction techniques Dec 18, 2002 Abandoned
Array ( [id] => 6712499 [patent_doc_number] => 20030172248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Synergetic computing system' [patent_app_type] => new [patent_app_number] => 10/296461 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10031 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 471 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20030172248.pdf [firstpage_image] =>[orig_patent_app_number] => 10296461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/296461
Synergetic computing system Dec 8, 2002 Abandoned
Array ( [id] => 6685019 [patent_doc_number] => 20030120883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Electronic processing device and method of pipelining in such a device' [patent_app_type] => new [patent_app_number] => 10/304369 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5600 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120883.pdf [firstpage_image] =>[orig_patent_app_number] => 10304369 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304369
Electronic processing device and method of pipelining in such a device Nov 25, 2002 Abandoned
Array ( [id] => 7365417 [patent_doc_number] => 20040015341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Programmable single-chip device and related development environment' [patent_app_type] => new [patent_app_number] => 10/296602 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3682 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015341.pdf [firstpage_image] =>[orig_patent_app_number] => 10296602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/296602
Programmable single-chip device and related development environment Nov 24, 2002 Abandoned
Array ( [id] => 513173 [patent_doc_number] => 07206927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Pipelined processor method and circuit with interleaving of iterative operations' [patent_app_type] => utility [patent_app_number] => 10/299412 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6324 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206927.pdf [firstpage_image] =>[orig_patent_app_number] => 10299412 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299412
Pipelined processor method and circuit with interleaving of iterative operations Nov 18, 2002 Issued
Array ( [id] => 563719 [patent_doc_number] => 07167973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Method and system for performing multi-tests in processors using results to set a register and indexing based on the register' [patent_app_type] => utility [patent_app_number] => 10/298247 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5262 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167973.pdf [firstpage_image] =>[orig_patent_app_number] => 10298247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298247
Method and system for performing multi-tests in processors using results to set a register and indexing based on the register Nov 14, 2002 Issued
Array ( [id] => 666983 [patent_doc_number] => 07103752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method and apparatus for broadcasting messages with set priority to guarantee knowledge of a state within a data processing system' [patent_app_type] => utility [patent_app_number] => 10/261865 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3791 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103752.pdf [firstpage_image] =>[orig_patent_app_number] => 10261865 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261865
Method and apparatus for broadcasting messages with set priority to guarantee knowledge of a state within a data processing system Sep 29, 2002 Issued
Array ( [id] => 7282307 [patent_doc_number] => 20040064684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'System and method for selectively updating pointers used in conditionally executed load/store with update instructions' [patent_app_type] => new [patent_app_number] => 10/262414 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7872 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064684.pdf [firstpage_image] =>[orig_patent_app_number] => 10262414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262414
System and method for selectively updating pointers used in conditionally executed load/store with update instructions Sep 29, 2002 Abandoned
Array ( [id] => 6685018 [patent_doc_number] => 20030120882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Apparatus and method for exiting from a software pipeline loop procedure in a digital signal processor' [patent_app_type] => new [patent_app_number] => 10/224711 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9453 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120882.pdf [firstpage_image] =>[orig_patent_app_number] => 10224711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224711
Apparatus and method for exiting from a software pipeline loop procedure in a digital signal processor Aug 20, 2002 Abandoned
Array ( [id] => 6685035 [patent_doc_number] => 20030120899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Apparatus and method for processing an interrupt in a software pipeline loop procedure in a digital signal processor' [patent_app_type] => new [patent_app_number] => 10/224786 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10721 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120899.pdf [firstpage_image] =>[orig_patent_app_number] => 10224786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224786
Apparatus and method for processing an interrupt in a software pipeline loop procedure in a digital signal processor Aug 20, 2002 Abandoned
Array ( [id] => 6685041 [patent_doc_number] => 20030120905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Apparatus and method for executing a nested loop program with a software pipeline loop procedure in a digital signal processor' [patent_app_type] => new [patent_app_number] => 10/224787 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10877 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120905.pdf [firstpage_image] =>[orig_patent_app_number] => 10224787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224787
Apparatus and method for executing a nested loop program with a software pipeline loop procedure in a digital signal processor Aug 20, 2002 Abandoned
Array ( [id] => 702132 [patent_doc_number] => 07073049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Non-copy shared stack and register file device and dual language processor structure using the same' [patent_app_type] => utility [patent_app_number] => 10/223295 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2191 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/073/07073049.pdf [firstpage_image] =>[orig_patent_app_number] => 10223295 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223295
Non-copy shared stack and register file device and dual language processor structure using the same Aug 19, 2002 Issued
Array ( [id] => 7608109 [patent_doc_number] => 07000091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'System and method for independent branching in systems with plural processing elements' [patent_app_type] => utility [patent_app_number] => 10/215095 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3002 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000091.pdf [firstpage_image] =>[orig_patent_app_number] => 10215095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215095
System and method for independent branching in systems with plural processing elements Aug 7, 2002 Issued
Array ( [id] => 7412519 [patent_doc_number] => 20040024992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Decoding method for a multi-length-mode instruction set' [patent_app_type] => new [patent_app_number] => 10/210075 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2026 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20040024992.pdf [firstpage_image] =>[orig_patent_app_number] => 10210075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210075
Decoding method for a multi-length-mode instruction set Aug 1, 2002 Abandoned
Array ( [id] => 7412633 [patent_doc_number] => 20040025004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Reconfigurable logic signal processor (RLSP) and method of configuring same' [patent_app_type] => new [patent_app_number] => 10/211738 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4891 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025004.pdf [firstpage_image] =>[orig_patent_app_number] => 10211738 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211738
Reconfigurable logic signal processor (RLSP) and method of configuring same Aug 1, 2002 Abandoned
Array ( [id] => 7445333 [patent_doc_number] => 20040003201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Division on an array processor' [patent_app_type] => new [patent_app_number] => 10/184514 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4635 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003201.pdf [firstpage_image] =>[orig_patent_app_number] => 10184514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184514
Division on an array processor Jun 27, 2002 Abandoned
Array ( [id] => 7603593 [patent_doc_number] => 07117346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Data processing system having multiple register contexts and method therefor' [patent_app_type] => utility [patent_app_number] => 10/159386 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5389 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117346.pdf [firstpage_image] =>[orig_patent_app_number] => 10159386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159386
Data processing system having multiple register contexts and method therefor May 30, 2002 Issued
Array ( [id] => 490297 [patent_doc_number] => 07222226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation' [patent_app_type] => utility [patent_app_number] => 10/135631 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11948 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222226.pdf [firstpage_image] =>[orig_patent_app_number] => 10135631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135631
System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation Apr 29, 2002 Issued
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