Search

Zachary J. Snyder

Examiner (ID: 914, Phone: (571)270-5291 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875, 2889
Total Applications
571
Issued Applications
340
Pending Applications
1
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1365781 [patent_doc_number] => 06581174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'On-chip testing circuit and method for integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/944750 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3219 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581174.pdf [firstpage_image] =>[orig_patent_app_number] => 09944750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944750
On-chip testing circuit and method for integrated circuits Aug 30, 2001 Issued
Array ( [id] => 1407917 [patent_doc_number] => 06560748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Encoding device' [patent_app_type] => B2 [patent_app_number] => 09/932243 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 7573 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560748.pdf [firstpage_image] =>[orig_patent_app_number] => 09932243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932243
Encoding device Aug 16, 2001 Issued
Array ( [id] => 5890409 [patent_doc_number] => 20020013925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Optical disc recording/reproducing method, optical disc and optical disc device' [patent_app_type] => new [patent_app_number] => 09/930529 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 12916 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013925.pdf [firstpage_image] =>[orig_patent_app_number] => 09930529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930529
Optical disc recording/reproducing method, optical disc and optical disc device Aug 14, 2001 Issued
Array ( [id] => 5877021 [patent_doc_number] => 20020049939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method and system for reliable broadcasting of data files and streams' [patent_app_type] => new [patent_app_number] => 09/922702 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6386 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20020049939.pdf [firstpage_image] =>[orig_patent_app_number] => 09922702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922702
Method and system for reliable broadcasting of data files and streams Aug 6, 2001 Issued
Array ( [id] => 1170571 [patent_doc_number] => 06766483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Semiconductor test apparatus' [patent_app_type] => B2 [patent_app_number] => 09/915756 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5585 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766483.pdf [firstpage_image] =>[orig_patent_app_number] => 09915756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915756
Semiconductor test apparatus Jul 25, 2001 Issued
Array ( [id] => 6062254 [patent_doc_number] => 20020031194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method and device for decoding convolutional codes' [patent_app_type] => new [patent_app_number] => 09/910341 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6878 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031194.pdf [firstpage_image] =>[orig_patent_app_number] => 09910341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910341
Method and device for decoding convolutional codes Jul 19, 2001 Issued
Array ( [id] => 1431993 [patent_doc_number] => 06516439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Error control apparatus and method using cyclic code' [patent_app_type] => B2 [patent_app_number] => 09/899062 [patent_app_country] => US [patent_app_date] => 2001-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9404 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516439.pdf [firstpage_image] =>[orig_patent_app_number] => 09899062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899062
Error control apparatus and method using cyclic code Jul 5, 2001 Issued
Array ( [id] => 1324315 [patent_doc_number] => 06611934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Boundary scan test cell circuit' [patent_app_type] => B2 [patent_app_number] => 09/898249 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 14441 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611934.pdf [firstpage_image] =>[orig_patent_app_number] => 09898249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898249
Boundary scan test cell circuit Jul 2, 2001 Issued
Array ( [id] => 6885469 [patent_doc_number] => 20010039634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Method of reducing test time for NVM cell-based FPGAs' [patent_app_type] => new [patent_app_number] => 09/880628 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4313 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039634.pdf [firstpage_image] =>[orig_patent_app_number] => 09880628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880628
Method of reducing test time for NVM cell-based FPGAs Jun 11, 2001 Abandoned
Array ( [id] => 6896759 [patent_doc_number] => 20010027549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method and apparatus for testing the timing of integrated circuits' [patent_app_type] => new [patent_app_number] => 09/877897 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4245 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027549.pdf [firstpage_image] =>[orig_patent_app_number] => 09877897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877897
Method and apparatus for testing the timing of integrated circuits Jun 7, 2001 Issued
Array ( [id] => 1456957 [patent_doc_number] => 06457153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Storage device and storage subsystem for efficiently writing error correcting code' [patent_app_type] => B2 [patent_app_number] => 09/861648 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3806 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457153.pdf [firstpage_image] =>[orig_patent_app_number] => 09861648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861648
Storage device and storage subsystem for efficiently writing error correcting code May 21, 2001 Issued
Array ( [id] => 7645852 [patent_doc_number] => 06477671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Semiconductor memory, memory device, and memory card' [patent_app_type] => B2 [patent_app_number] => 09/845350 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 68 [patent_no_of_words] => 23095 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477671.pdf [firstpage_image] =>[orig_patent_app_number] => 09845350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845350
Semiconductor memory, memory device, and memory card Apr 30, 2001 Issued
Array ( [id] => 984768 [patent_doc_number] => 06928597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and apparatus for testing digital circuitry' [patent_app_type] => utility [patent_app_number] => 09/825279 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1568 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928597.pdf [firstpage_image] =>[orig_patent_app_number] => 09825279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825279
Method and apparatus for testing digital circuitry Apr 2, 2001 Issued
Array ( [id] => 6901911 [patent_doc_number] => 20010023494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'BIP-N processing apparatus and BIP-N processing method therefor' [patent_app_type] => new [patent_app_number] => 09/808065 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3171 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023494.pdf [firstpage_image] =>[orig_patent_app_number] => 09808065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808065
BIP-N processing apparatus and BIP-N processing method therefor Mar 13, 2001 Abandoned
Array ( [id] => 5971534 [patent_doc_number] => 20020091932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Qualification authentication method using variable authentication information' [patent_app_type] => new [patent_app_number] => 09/766305 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7176 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091932.pdf [firstpage_image] =>[orig_patent_app_number] => 09766305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766305
Qualification authentication method using variable authentication information Jan 18, 2001 Abandoned
Array ( [id] => 7041538 [patent_doc_number] => 20010005896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'On-board testing circuit and method for improving testing of integrated circuits' [patent_app_type] => new-utility [patent_app_number] => 09/764568 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4032 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005896.pdf [firstpage_image] =>[orig_patent_app_number] => 09764568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764568
On-board testing circuit and method for improving testing of integrated circuits Jan 15, 2001 Issued
Array ( [id] => 4333884 [patent_doc_number] => 06317857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'System and method for utilizing checksums to recover data' [patent_app_type] => 1 [patent_app_number] => 9/759853 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10186 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317857.pdf [firstpage_image] =>[orig_patent_app_number] => 759853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759853
System and method for utilizing checksums to recover data Jan 11, 2001 Issued
Array ( [id] => 1407702 [patent_doc_number] => 06560736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for diagnosing bridging faults in integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/758303 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 17382 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560736.pdf [firstpage_image] =>[orig_patent_app_number] => 09758303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758303
Method for diagnosing bridging faults in integrated circuits Jan 9, 2001 Issued
Array ( [id] => 6890741 [patent_doc_number] => 20010007972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'Method and apparatus for verifying adequacy of test patterns' [patent_app_type] => new-utility [patent_app_number] => 09/754171 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5858 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20010007972.pdf [firstpage_image] =>[orig_patent_app_number] => 09754171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754171
Method and apparatus for verifying adequacy of test patterns Jan 2, 2001 Abandoned
Array ( [id] => 6294398 [patent_doc_number] => 20020056039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'System for providing certification confirming agency service using double electronic signature' [patent_app_type] => new [patent_app_number] => 09/750493 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3771 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056039.pdf [firstpage_image] =>[orig_patent_app_number] => 09750493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750493
System for providing certification confirming agency service using double electronic signature Dec 27, 2000 Abandoned
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