Zachary K. Huson

Array ( [id] => 18677801 [patent_doc_number] => 20230315448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => FLEXIBLE SUPPORT FOR DEVICE EMULATION AND BANK SWAPPING [patent_app_type] => utility [patent_app_number] => 17/708882 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19212785 [patent_doc_number] => 12001848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Microprocessor with time counter for statically dispatching instructions with phantom registers [patent_app_type] => utility [patent_app_number] => 17/704614 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7900 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18659836 [patent_doc_number] => 20230305843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PROCESSOR MICRO-OPERATIONS CACHE ARCHITECTURE FOR INTERMEDIATE INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/704127 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18651579 [patent_doc_number] => 20230297415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => APPARATUS AND METHOD FOR SCHEDULING INFERENCE TASKS [patent_app_type] => utility [patent_app_number] => 17/699058 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539383 [patent_doc_number] => 20230244491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MULTI-THREADING MICROPROCESSOR WITH A TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/697870 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539381 [patent_doc_number] => 20230244489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => TIME-RESOURCE MATRIX FOR A MICROPROCESSOR WITH TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/697865 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17674946 [patent_doc_number] => 20220188113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => LOOK-UP TABLE WRITE [patent_app_type] => utility [patent_app_number] => 17/686584 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18592033 [patent_doc_number] => 11740931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Processing device, control unit, electronic device, method for the electronic device, and computer program for the electronic device [patent_app_type] => utility [patent_app_number] => 17/651906 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8978 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539385 [patent_doc_number] => 20230244493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => REGISTER SCOREBOARD FOR A MICROPROCESSOR WITH A TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/672622 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539382 [patent_doc_number] => 20230244490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MICROPROCESSOR WITH TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/588315 [patent_app_country] => US [patent_app_date] => 2022-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19137864 [patent_doc_number] => 11972835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Latch circuit device and port sampling system [patent_app_type] => utility [patent_app_number] => 17/582705 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3624 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18386190 [patent_doc_number] => 11656971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Technology for dynamically tuning processor features [patent_app_type] => utility [patent_app_number] => 17/582051 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18519786 [patent_doc_number] => 11709677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Look-up table initialize [patent_app_type] => utility [patent_app_number] => 17/577482 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 23673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17751587 [patent_doc_number] => 20220229792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SERIAL INTERRUPT METHOD, DEVICE, SERIAL INTERRUPT PROCESSING METHOD, AND PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/575212 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17535358 [patent_doc_number] => 20220113967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ACCELERATOR FABRIC FOR DISCRETE GRAPHICS [patent_app_type] => utility [patent_app_number] => 17/561197 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18303349 [patent_doc_number] => 11625251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-11 [patent_title] => Mechanism for reducing coherence directory controller overhead for near-memory compute elements [patent_app_type] => utility [patent_app_number] => 17/561112 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18438280 [patent_doc_number] => 20230185575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => VLIW Power Management [patent_app_type] => utility [patent_app_number] => 17/550878 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18527657 [patent_doc_number] => 11714648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Systems for performing instructions to quickly convert and use tiles as 1D vectors [patent_app_type] => utility [patent_app_number] => 17/549221 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 46 [patent_no_of_words] => 27137 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19093028 [patent_doc_number] => 11954489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Systems for performing instructions to quickly convert and use tiles as 1D vectors [patent_app_type] => utility [patent_app_number] => 17/549363 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 46 [patent_no_of_words] => 27167 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18218215 [patent_doc_number] => 11593153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Directed interrupt virtualization with interrupt table [patent_app_type] => utility [patent_app_number] => 17/643910 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 25869 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643910 [rel_patent_id] =>[rel_patent_doc_number] =>)