Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19071360 [patent_doc_number] => 20240105786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/097253 [patent_app_country] => US [patent_app_date] => 2023-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097253
Semiconductor device structure and methods of forming the same Jan 14, 2023 Issued
Array ( [id] => 19321490 [patent_doc_number] => 20240243037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STRUCTURE WITH AIR GAPS EXTENDING FROM DIELECTRIC LINER AROUND THROUGH SEMICONDCUTOR VIA [patent_app_type] => utility [patent_app_number] => 18/154481 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154481
Structure with air gaps extending from dielectric liner around through semicondcutor via Jan 12, 2023 Issued
Array ( [id] => 20760061 [patent_doc_number] => 12652853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Semiconductor structure having plurality of fin segments and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/152448 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 64 [patent_no_of_words] => 9166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152448
Semiconductor structure having plurality of fin segments and method for forming the same Jan 9, 2023 Issued
Array ( [id] => 18680132 [patent_doc_number] => 20230317790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Semiconductor Device having Doped Gate Dielectric Layer and Method for Forming the Same [patent_app_type] => utility [patent_app_number] => 18/152601 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152601 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152601
Semiconductor device having doped gate dielectric layer and method for forming the same Jan 9, 2023 Issued
Array ( [id] => 20404464 [patent_doc_number] => 12494445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Radiofrequency filter and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/094397 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1116 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094397
Radiofrequency filter and manufacturing method thereof Jan 8, 2023 Issued
Array ( [id] => 19016487 [patent_doc_number] => 11923432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 18/149224 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 12061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149224 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149224
Semiconductor device and method Jan 2, 2023 Issued
Array ( [id] => 19912503 [patent_doc_number] => 12288722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Spacer structure for semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/149130 [patent_app_country] => US [patent_app_date] => 2023-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149130
Spacer structure for semiconductor device and method for forming the same Jan 1, 2023 Issued
Array ( [id] => 18349180 [patent_doc_number] => 20230137291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => DIFFUSION LAYER FOR MAGNETIC TUNNEL JUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/148829 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148829
Diffusion barrier layer on interconnection vias for magnetic tunnel junctions Dec 29, 2022 Issued
Array ( [id] => 19285558 [patent_doc_number] => 20240222035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => PACKAGE SUBSTRATE EMBEDDED MULTI-LAYERED IN VIA CAPACITORS [patent_app_type] => utility [patent_app_number] => 18/090305 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090305
PACKAGE SUBSTRATE EMBEDDED MULTI-LAYERED IN VIA CAPACITORS Dec 27, 2022 Pending
Array ( [id] => 20441575 [patent_doc_number] => 12512417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Method and structure for determining an overlay error [patent_app_type] => utility [patent_app_number] => 18/068839 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068839
Method and structure for determining an overlay error Dec 19, 2022 Issued
Array ( [id] => 18326786 [patent_doc_number] => 20230124914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHOD FOR FORMING SIDEWALL SPACERS AND SEMICONDUCTOR DEVICES FABRICATED THEREOF [patent_app_type] => utility [patent_app_number] => 18/084051 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084051
Method for forming sidewall spacers and semiconductor devices fabricated thereof Dec 18, 2022 Issued
Array ( [id] => 19444658 [patent_doc_number] => 12094950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Nanostructures and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/066555 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 113 [patent_no_of_words] => 10828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066555
Nanostructures and method for manufacturing the same Dec 14, 2022 Issued
Array ( [id] => 18310530 [patent_doc_number] => 20230114430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => NON-VOLATILE MEMORY DEVICE WITH REDUCED AREA [patent_app_type] => utility [patent_app_number] => 18/066290 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066290
Non-volatile memory device with reduced area Dec 14, 2022 Issued
Array ( [id] => 18285718 [patent_doc_number] => 20230101190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SEMICONDUCTOR CONTINUOUS ARRAY LAYER [patent_app_type] => utility [patent_app_number] => 18/077234 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077234
SEMICONDUCTOR CONTINUOUS ARRAY LAYER Dec 7, 2022 Abandoned
Array ( [id] => 20801315 [patent_doc_number] => 20260182235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-25 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/713205 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18713205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/713205
DISPLAY PANEL AND DISPLAY DEVICE Nov 28, 2022 Pending
Array ( [id] => 19370486 [patent_doc_number] => 12062580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/991735 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 41 [patent_no_of_words] => 12408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991735
Method of manufacturing a semiconductor device and a semiconductor device Nov 20, 2022 Issued
Array ( [id] => 18270231 [patent_doc_number] => 20230091473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => Multilayer Diamond Display System and Method [patent_app_type] => utility [patent_app_number] => 17/990368 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990368
Multilayer Diamond Display System and Method Nov 17, 2022 Pending
Array ( [id] => 20734597 [patent_doc_number] => 12641862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Three-dimensional cross field effect self-aligned transistors with frontside and backside power connections [patent_app_type] => utility [patent_app_number] => 18/055341 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055341
Three-dimensional cross field effect self-aligned transistors with frontside and backside power connections Nov 13, 2022 Issued
Array ( [id] => 20205590 [patent_doc_number] => 12408386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Thin film transistor array substrate including an active layer having two different channel areas and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/985634 [patent_app_country] => US [patent_app_date] => 2022-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9112 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/985634
Thin film transistor array substrate including an active layer having two different channel areas and electronic device including the same Nov 10, 2022 Issued
Array ( [id] => 18456246 [patent_doc_number] => 20230197528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => VIA FORMATION IN AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/054228 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054228
Conductive via formation connecting transistor structures in an integrated circuit Nov 9, 2022 Issued
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