Search

Zachary W. Wilkes

Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
1061
Issued Applications
667
Pending Applications
96
Abandoned Applications
322

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17933232 [patent_doc_number] => 20220328358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => Semiconductor Method and Device [patent_app_type] => utility [patent_app_number] => 17/843694 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843694
Semiconductor method and device Jun 16, 2022 Issued
Array ( [id] => 18229938 [patent_doc_number] => 20230068932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/842890 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842890
Semiconductor device including plurality of gate fingers with various levels Jun 16, 2022 Issued
Array ( [id] => 18141021 [patent_doc_number] => 20230014863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/841151 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841151
Display device having fan-out area and line protection configuration Jun 14, 2022 Issued
Array ( [id] => 19906564 [patent_doc_number] => 12283583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Display device including plurality of light-emitting elements with different emission wavelength variations [patent_app_type] => utility [patent_app_number] => 17/841043 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5292 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841043
Display device including plurality of light-emitting elements with different emission wavelength variations Jun 14, 2022 Issued
Array ( [id] => 19796285 [patent_doc_number] => 12237254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor device including wiring substrate having multiple signal wirings and multiple insulating layers [patent_app_type] => utility [patent_app_number] => 17/841196 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10416 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841196
Semiconductor device including wiring substrate having multiple signal wirings and multiple insulating layers Jun 14, 2022 Issued
Array ( [id] => 18209673 [patent_doc_number] => 20230055933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MEMORY DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/806793 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806793
Memory device and forming method thereof Jun 13, 2022 Issued
Array ( [id] => 17886840 [patent_doc_number] => 20220302318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => DEVICES INCLUDING VERTICAL TRANSISTORS, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/806427 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806427
Devices including vertical transistors, and related methods Jun 9, 2022 Issued
Array ( [id] => 18178093 [patent_doc_number] => 20230038822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => DUAL SILICIDE LAYERS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/833607 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833607
Dual silicide layers in semiconductor devices Jun 5, 2022 Issued
Array ( [id] => 18821340 [patent_doc_number] => 20230395681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/832651 [patent_app_country] => US [patent_app_date] => 2022-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832651
Multi-gate device including semiconductor fin between dielectric fins and method of fabrication thereof Jun 4, 2022 Issued
Array ( [id] => 19421119 [patent_doc_number] => 20240297243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => Tunneling Field Effect Transistor and Manufacturing Method Thereof, Display Panel and Display Apparatus [patent_app_type] => utility [patent_app_number] => 18/026833 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18026833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/026833
Tunneling field effect transistor and manufacturing method thereof, display panel and display apparatus May 26, 2022 Issued
Array ( [id] => 18967455 [patent_doc_number] => 11901235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Ion implantation for nano-FET [patent_app_type] => utility [patent_app_number] => 17/824610 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 73 [patent_no_of_words] => 15345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824610
Ion implantation for nano-FET May 24, 2022 Issued
Array ( [id] => 20307125 [patent_doc_number] => 12453136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate [patent_app_type] => utility [patent_app_number] => 17/824812 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 1170 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824812
Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate May 24, 2022 Issued
Array ( [id] => 17855182 [patent_doc_number] => 20220285225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Integrated Circuit Device With Low Threshold Voltage [patent_app_type] => utility [patent_app_number] => 17/750579 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750579
Integrated circuit device with low threshold voltage May 22, 2022 Issued
Array ( [id] => 20332854 [patent_doc_number] => 12463139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Apparatus and method for fabricating multi-die interconnection using lithography process [patent_app_type] => utility [patent_app_number] => 17/746806 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 2680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746806
Apparatus and method for fabricating multi-die interconnection using lithography process May 16, 2022 Issued
Array ( [id] => 18161057 [patent_doc_number] => 20230027649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => DISPLAY APPARATUS INCLUDING DISPLAY MODULE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/745458 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745458
Display apparatus including display module with anisotropic conductive layer, front cover and side cover, and manufacturing method thereof May 15, 2022 Issued
Array ( [id] => 17833846 [patent_doc_number] => 20220271150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/743947 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743947
Method for manufacturing semiconductor device May 12, 2022 Issued
Array ( [id] => 18548407 [patent_doc_number] => 11721769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Semiconductor device and display device including the same [patent_app_type] => utility [patent_app_number] => 17/743956 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 181 [patent_no_of_words] => 65636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743956
Semiconductor device and display device including the same May 12, 2022 Issued
Array ( [id] => 17840694 [patent_doc_number] => 20220278000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Multi-Layered Insulating Film Stack [patent_app_type] => utility [patent_app_number] => 17/663321 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663321
Multi-layered insulating film stack May 12, 2022 Issued
Array ( [id] => 18840162 [patent_doc_number] => 11848241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Semiconductor structure and related methods [patent_app_type] => utility [patent_app_number] => 17/662492 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 9207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662492
Semiconductor structure and related methods May 8, 2022 Issued
Array ( [id] => 18967456 [patent_doc_number] => 11901236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor structure with gate-all-around devices and stacked FinFET devices [patent_app_type] => utility [patent_app_number] => 17/739925 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739925
Semiconductor structure with gate-all-around devices and stacked FinFET devices May 8, 2022 Issued
Menu