
Zachary W. Wilkes
Examiner (ID: 2151, Phone: (571)270-7540 , Office: P/2872 )
| Most Active Art Unit | 2872 |
| Art Unit(s) | 2873, 2872 |
| Total Applications | 1061 |
| Issued Applications | 667 |
| Pending Applications | 96 |
| Abandoned Applications | 322 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19515903
[patent_doc_number] => 20240347589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/633791
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10062
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633791
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/633791 | SEMICONDUCTOR DEVICE | Apr 11, 2024 | Pending |
Array
(
[id] => 19837473
[patent_doc_number] => 20250089259
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/631225
[patent_app_country] => US
[patent_app_date] => 2024-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2553
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631225
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/631225 | NON-VOLATILE MEMORY | Apr 9, 2024 | Pending |
Array
(
[id] => 19945452
[patent_doc_number] => 12317602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Forming ESD devices using multi-gate compatible processes
[patent_app_type] => utility
[patent_app_number] => 18/623294
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 44
[patent_no_of_words] => 6948
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623294
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623294 | Forming ESD devices using multi-gate compatible processes | Mar 31, 2024 | Issued |
Array
(
[id] => 20283925
[patent_doc_number] => 20250309167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => CONDUCTIVE POST WITH FOOTING PROFILE
[patent_app_type] => utility
[patent_app_number] => 18/621673
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1089
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621673
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/621673 | CONDUCTIVE POST WITH FOOTING PROFILE | Mar 28, 2024 | Pending |
Array
(
[id] => 19321642
[patent_doc_number] => 20240243189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => ISOLATION STRUCTURES FOR TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 18/622018
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622018
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/622018 | ISOLATION STRUCTURES FOR TRANSISTORS | Mar 28, 2024 | Pending |
Array
(
[id] => 19305905
[patent_doc_number] => 20240234485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/614935
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614935
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614935 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME | Mar 24, 2024 | Pending |
Array
(
[id] => 19484129
[patent_doc_number] => 20240332171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => INSULATION CHIP AND SIGNAL TRANSMISSION DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/614921
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614921
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614921 | INSULATION CHIP AND SIGNAL TRANSMISSION DEVICE | Mar 24, 2024 | Pending |
Array
(
[id] => 20251251
[patent_doc_number] => 20250300120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => Wafer Level Land Grid Array
[patent_app_type] => utility
[patent_app_number] => 18/614332
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614332
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614332 | Wafer Level Land Grid Array | Mar 21, 2024 | Pending |
Array
(
[id] => 19364188
[patent_doc_number] => 20240266222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/613772
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 40363
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613772
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/613772 | Manufacturing method of semiconductor device including mulitple oxides | Mar 21, 2024 | Issued |
Array
(
[id] => 20235842
[patent_doc_number] => 20250293161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-18
[patent_title] => SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN CONTACT MOL CUT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/606689
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606689
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606689 | SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN CONTACT MOL CUT STRUCTURE | Mar 14, 2024 | Pending |
Array
(
[id] => 19269394
[patent_doc_number] => 20240213098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => Gate Oxide Structures In Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 18/600216
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600216
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600216 | Plural gate oxide structures with different thicknesses in semiconductor devices | Mar 7, 2024 | Issued |
Array
(
[id] => 19269638
[patent_doc_number] => 20240213342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/599522
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599522
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/599522 | Semiconductor device having contact structure including lower contact pattern and upper contact pattern between line structures | Mar 7, 2024 | Issued |
Array
(
[id] => 19271523
[patent_doc_number] => 20240215230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => MEMORY DEVICE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/596115
[patent_app_country] => US
[patent_app_date] => 2024-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596115
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/596115 | Semiconductor device including alternating semiconductor layers with different widths and method for forming the same | Mar 4, 2024 | Issued |
Array
(
[id] => 19271510
[patent_doc_number] => 20240215217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => VERTICAL HETEROSTRUCTURE SEMICONDUCTOR MEMORY CELL AND METHODS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/596501
[patent_app_country] => US
[patent_app_date] => 2024-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596501
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/596501 | VERTICAL HETEROSTRUCTURE SEMICONDUCTOR MEMORY CELL AND METHODS FOR MAKING THE SAME | Mar 4, 2024 | Pending |
Array
(
[id] => 19589856
[patent_doc_number] => 20240387413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/592266
[patent_app_country] => US
[patent_app_date] => 2024-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13548
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592266
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/592266 | SEMICONDUCTOR DEVICE | Feb 28, 2024 | Pending |
Array
(
[id] => 19912605
[patent_doc_number] => 12288824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-29
[patent_title] => Semiconductor device including top-gate bottom-contact transistor
[patent_app_type] => utility
[patent_app_number] => 18/589607
[patent_app_country] => US
[patent_app_date] => 2024-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 42
[patent_no_of_words] => 19626
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589607
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/589607 | Semiconductor device including top-gate bottom-contact transistor | Feb 27, 2024 | Issued |
Array
(
[id] => 20754798
[patent_doc_number] => 20260157031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-06-04
[patent_title] => DISPLAY PANELS AND DISPLAY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/697457
[patent_app_country] => US
[patent_app_date] => 2024-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3397
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 345
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18697457
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/697457 | DISPLAY PANELS AND DISPLAY DEVICES | Feb 26, 2024 | Pending |
Array
(
[id] => 20196842
[patent_doc_number] => 20250273552
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => Semiconductor Device and Method of Forming Encapsulated Vertical Interconnect Structure
[patent_app_type] => utility
[patent_app_number] => 18/587875
[patent_app_country] => US
[patent_app_date] => 2024-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 959
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587875
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/587875 | Semiconductor Device and Method of Forming Encapsulated Vertical Interconnect Structure | Feb 25, 2024 | Pending |
Array
(
[id] => 19926290
[patent_doc_number] => 12300584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Semiconductor device including heat sink with exposed side from encapsulant and a method of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 18/587836
[patent_app_country] => US
[patent_app_date] => 2024-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 49
[patent_no_of_words] => 6238
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587836
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/587836 | Semiconductor device including heat sink with exposed side from encapsulant and a method of manufacturing thereof | Feb 25, 2024 | Issued |
Array
(
[id] => 19407308
[patent_doc_number] => 20240290819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/586222
[patent_app_country] => US
[patent_app_date] => 2024-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586222
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/586222 | DISPLAY DEVICE | Feb 22, 2024 | Pending |